Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UDOT (vector, 8B)

Test 1: uops

Code:

  udot v0.2s, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230008525482510001000100039831303018303730372415328951000100030003037303711100110000000073116112630100030383038303830383038
10043037240006125482510001000100039831303018303730372415328951000100030003037303711100110000000073116112630100030383038303830383038
10043037230006125482510001000100039831303018303730372415328951000100030003037303711100110000000073116112630100030383038303830383038
1004303723014106125482510001000100039831313018303730372415328951000100030003037303721100110000000073116112630100030383038303830383038
10043037240008225482510001000100039831313018303730372415328951000100030003037303711100110000000073116112630100030383038303830383038
10043037230006125482510001000100039831303018303730372415328951000100030003037303711100110000000073116112630100030383038303830383038
10043037240006125482510001000100039831313018303730372415328951000100030003037303711100110000000373116112630100030383038303830383038
10043037240006125482510001000100039831303018303730372415328951000100030003037303711100110000000073116112630100030383038303830383038
10043037230006125482510001000100039831303018303730372415328951000100030003037303711100110000000073116112838100030383038303830383038
10043037230006125482510001000100039831303018303730372415328951000100030003037303711100110000000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  udot v0.2s, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723200006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710031643296340100001003003830038300383003830038
102043003723300006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710031633296340100001003003830038300383003830038
102043003723300008429548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710031634296340100001003003830038300383003830038
102043003723200008429548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710031633296340100001003003830038300383003830038
1020430037233000062829548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710031643296340100001003003830038300383003830038
102043003723300006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710031633296340100001003003830038300383003830038
102043003723300006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710031633296340100001003003830038300383003830038
102043003723300006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710031633296340100001003003830038300383003830038
102043003723300006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710031633296340100001003003830038300383003830038
102043003723300006129548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100000710031633296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003723300397295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000006403162229630010000103003830038300383003830038
100243003723200140295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037233012822954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010086006402162229630010000103003830038300383003830038
10024300372330061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003723200127295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001001006402162229630010000103003830038300383003830038
10024300372330121130295486410018101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001002006402162229630010000103003830038300383003830038
100243003723300666295484410010101000810100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001001006402162229630010000103003830038300383003830038
100243003723300929295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000606402173229630010000103003830038300383003830038
1002430037232001082295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000906402162229648010000103003830038300383003830038
100243003723300128295488310010101000010100005042773130300903013130037283013287671001024101622030000300373003711100211091010100001000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  udot v0.2s, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037232000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296670100001003003830038300383003830038
1020430037233000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037233000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037232000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037233000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037233000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011621296340100001003003830038300383003830038
1020430037232000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372330000000357295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
1020430037232000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003723312612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372320612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372330612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010100640216222963010000103003830038300383003830038
10024300372330612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372330612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222970210000103003830038300383003830038
10024300372330612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372320612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010100640216222963010000103003830038300383003830038
10024300372330612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010100640216222963010000103003830038300383003830038
10024300372330612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372330612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  udot v0.2s, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723300000023229548251010010010000100100005004277313003001830037300372827262874110100200100082003002430037300371110201100991001001000010000000002111718001600296460100001003003830038300383003830038
102043003722400000076829548251010010010000100100005004277313103001830037300372827232874510100200100002003000030037300371110201100991001001000010000000000000710011611296340100001003003830038300383003830038
102043003722500000061295482510100100100001001000050042773130030018300373003728265328745101002001000020030000300373003711102011009910010010000100000010000007100116112963424100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010000000002000710011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010000000004000710011611296340100001003003830038300383003830038
102043003722500000015629530251010010010000100100005004277313003001830037300372826532879810100200100002003000030037300371110201100991001001000010000000000000710011611296340100001003018130038300383003830038
102043003722500012006129548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010000000090000710011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313003001830037300372827532874510100200100002003000030037300371110201100991001001000010000003060000710011611296340100001003003830038300383003830038
1020430037225000000270029548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010001000000000710011611296340100001003003830038300383003830038
102043003722500000025229548251010010010000100100005004277313003001830037300372826532874510100200100002003000030037300371110201100991001001000010000000000000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037233051612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372330302512954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372330151312954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010106402162229666010000103008630085300853003830038
1002430037232003382954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010036402162229630010000103003830038300383003830038
100243003723300612954825100101010000101000050427731313001830037300372828732876710010201017220300003003730037111002110910101000010006402162229630110000103003830038300383003830038
100243003723300612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003723300612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003723300842954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037233065362954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003723300612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010036402162229630010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  udot v0.2s, v8.8b, v9.8b
  movi v1.16b, 0
  udot v1.2s, v8.8b, v9.8b
  movi v2.16b, 0
  udot v2.2s, v8.8b, v9.8b
  movi v3.16b, 0
  udot v3.2s, v8.8b, v9.8b
  movi v4.16b, 0
  udot v4.2s, v8.8b, v9.8b
  movi v5.16b, 0
  udot v5.2s, v8.8b, v9.8b
  movi v6.16b, 0
  udot v6.2s, v8.8b, v9.8b
  movi v7.16b, 0
  udot v7.2s, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042006515500000000003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000000030000101112161120061001600001002006520065200652006520065
1602042006415500000000006725801001008000010080000500640000120045200642006432280100200800002002400002006420064111602011009910010016000010000006060000101111161120061001600001002006520065200652006520065
160204200641550000000000392580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000000401260000101111161120061001600001002006520065200652006520065
16020420064155000000000039258010010080000100800005006400000200452006420064712801282008000020024000020064200641116020110099100100160000100000026000000101111161120061001600001002006520065200652006520065
160204200641550000000000392580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000000001350000101111161120061001600001002006520065200652006520065
16020420064156000000000039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100000031000000101111161120061001600001002006520065200652006520065
1602042006415500000000003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000001060000101111161120061001600001002006520065200652006520065
16020420064155000000000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000027060000101111161120061001600001002006520065200652006520065
16020420064155000000000039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100000027030000101111161120061001600001002006520065200652006520065
16020420064155000000000039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100000037000000101111161120061001600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6erob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420065155000000000512580012128000012800006264000011200272004620046032280012208000020240000200462004611160021109101016000010000601002732292021153200482150160000102005120051200512005120051
16002420046156000000000452580012128000012800006264000001200272004620046032280012208000020240000200462005011160021109101016000010000001003131152442193200432150160000102004720047200472004720047
16002420050156000000000452580012128000012800006264000011200312005020046032280012208000020240000200502005011160021109101016000010000001002731132021149200432300160000102004720047200472004720047
16002420051156000000600512580012128000012800006264000001200272004620050032280012208000020240000200502005011160021109101016000010000001002932162441195200472150160000102004720051200472004720051
16002420046155000000000512580012128000012800006264000011200312004620046032280012208000020240000200472004611160021109101016000010000001003162295742239200472300160000102005120051200512005120051
16002420050150000000000452580012128000012800006264000011200312005020050032280012208000020240000200502005011160021109101016000010000001002831132021155200432150160000102004720047200472004720047
1600242004615000000024900452580012128000012800006264000011200272005020046032280012208000020240000200502004611160021109101016000010000001003232192421135200432150160000102005120047200472005120047
160024200501500000000003302580012128000012800006264000011200272004620046032280012208000020240000200462004611160021109101016000010000001003231132021193200432150160000102004720047200472004720047
1600242004615000000000171872780012128000012800006264000001200322006020060032280012208000020240000200602005111160021109101016000010000001002631142522293200572402160000102005220052200522005220052
16002420051150100000000452980012128000012800006264000001200412005120051032280012208000020240000200512005111160021109101016000010000001002831192521153200482401160000102006120052200522005220061

Test 6: throughput

Count: 16

Code:

  udot v0.2s, v16.8b, v17.8b
  udot v1.2s, v16.8b, v17.8b
  udot v2.2s, v16.8b, v17.8b
  udot v3.2s, v16.8b, v17.8b
  udot v4.2s, v16.8b, v17.8b
  udot v5.2s, v16.8b, v17.8b
  udot v6.2s, v16.8b, v17.8b
  udot v7.2s, v16.8b, v17.8b
  udot v8.2s, v16.8b, v17.8b
  udot v9.2s, v16.8b, v17.8b
  udot v10.2s, v16.8b, v17.8b
  udot v11.2s, v16.8b, v17.8b
  udot v12.2s, v16.8b, v17.8b
  udot v13.2s, v16.8b, v17.8b
  udot v14.2s, v16.8b, v17.8b
  udot v15.2s, v16.8b, v17.8b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)18191e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044007331000001194251601171001600001001600005001280000040020400394003919973032000616010020016000020048000040049400391116020110099100100160000100001011011612400361600001004004040040400404004040040
1602044004831000001741251601181001600001001600005001280000040029400394004019973032000616010020016000020048000040049400491116020110099100100160000100001011021611400361600001004004040041400414004140094
1602044004831000000173251601001001600001001600005002399082040021400394003919973032000616010020016000020048000040039400391116020110099100100160000100001011011611400371600001004004940040400504004140088
1602044003931000001741251601001001600001001600005001280000140029400394003919973031999716010020016000020048000040039400391116020110099100100160000100001011021611400361600001004004040040400494004040049
1602044003931000001741251601171001600001001600005001320000140029400394003919973031999716010020016000020048000040039400481116020110099100100160000100001011011611400371600001004004940040400404004040040
160204400483100000051251601001001600001001600005001280000040029400484003919973031999816010020016000020048000040039400401116020110099100100160000100001011011611400361600001004004040049400494004040040
1602044003931000001741251601171001600001001600005001280000140029400394003919973032000616010020016000020048000040039400391116020110099100100160000100001011011611400361600001004004040049400534004040049
160204400393100000041251601171001600171001600005001280000140029400984003919973032000616010020016000020048000040048400391116020110099100100160000100001011011611400361600001004011540101400404004940167
160204400393100000050251601001001600171001600005001280000040254400974004819973071999716024120016000020248000040048401103116020110099100100160000100001011021612400361600001004004040040400404004940040
16020440048310000017716251601001001600171001600005002398999040020400394003919973031999716010020016000020048000040048400391116020110099100100160000100131011021622400361600001004004940040400404004940040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f373a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5e5f6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2c9cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244003931000000003226325160010101600001016000050128000001154002004003940039199963200191600102016000020480000400494003911160021109101016000010000010024811151621161740036155160000104004040040400404004040040
160024400393100000000177825160028101600001016000050128000001154002004003940039199963200191600102016000020480000400394003911160021109101016000010004010022841161621171740036155160000104004040040400404004940040
16002440039310000000181615325160010101600181016000050128000000154002004003940039199963200191600102016000020480000400394003911160021109101016000010000010022841161622161740037155160000104019340049400494004040040
16002440039311000098801322725160010101600001016000050128000001154003004003940049199963200191600102016000020480000400394003911160021109101016000010000010022114161641216640036305160000104004040040400404004040040
1600244003931000000001152251600101016000010160000501280000001540020340049400491999632001916001020160000204800004003940049111600211091010160000100020100221151161622271740036155160000104004040040400404004040040
1600244003931000000017115525160010101600001016000050243886501154002004003940039199963200191600102016000020480000400484003911160021109101016000010000010022852161621217640036156160000104004040040400404004040040
160024400483100000000115525160010101600001016000050131999701154002004003940039199963200291600102016000020480000400394003911160021109101016000010000010022841161621117640100305160000104004940040400404004040040
160024400393110000001705225160010101600001016000050128000001104002004004040048199963200191600102016000020480000400404004011160021109101016000010000010024312161641216640036406160000104004040040400404004040040
160024400393110000000052251600101016000010160000501280000001040020040039400391999632001916001020160000204800004003940039111600211091010160000100000100226211616422717400464012160000104004040040400404004040049
1600244003931000000000952516002810160000101600005012800000010400200400394003919996320029160010201600002048000040039400391116002110910101600001000001002462161642216640036406160000104004040040400404004040040