Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UHADD (vector, 4H)

Test 1: uops

Code:

  uhadd v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000094116111787100020382038203820382038
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203716082168725100010001000264680201820372037157231895100010002000203720371110011000373116111787100020382038203820382038
1004203715082168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uhadd v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000573196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100027101161119846100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100057101161119791100001002003820038200382003820038
102042003715000235196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000168196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100427101161119791100001002003820038200382003820038
102042003715000149196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000103196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000124196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100037101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820086200382003820038
102042003715000149196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000020719687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
100242003715000009008219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
1002420037150000000016619687251001010100001110152502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000064031622197850010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
1002420037150000000026919687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000003064021622197850010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uhadd v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715008419687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100671011611197910100001002003820038200382003820038
1020420037150014919687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150019119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150017219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500536196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037156061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216321978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uhadd v0.4h, v8.4h, v9.4h
  uhadd v1.4h, v8.4h, v9.4h
  uhadd v2.4h, v8.4h, v9.4h
  uhadd v3.4h, v8.4h, v9.4h
  uhadd v4.4h, v8.4h, v9.4h
  uhadd v5.4h, v8.4h, v9.4h
  uhadd v6.4h, v8.4h, v9.4h
  uhadd v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051102161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815006325801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815094025801001228000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050201116222003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216362003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020316262003580000102003920039200392003920039
8002420038150006025800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216222003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100458001020800002016000020038200381180021109101080000100005020216222003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216622003580000102003920039200392003920039
80024200381500060925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216622003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216622003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216222003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100015020216222003580000102003920039200392003920039