Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UHADD (vector, 4S)

Test 1: uops

Code:

  uhadd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000373216221787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715961168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000673216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  uhadd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150017019687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150021419687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011612197910100001002003820038202272003820038
1020420037150014519687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003714906119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011612197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011612197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715008219687251010010010000100100005002847680020018200372003718441318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150016619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150034619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150922119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162319785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162419785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162319785010000102003820038200382003820038
1002420037150035519687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162519785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162419785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162419785010000102003820038200382003820038
1002420037150016819687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000104006402162219785010000102003820038200382003820038
1002420037150023219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162319785010000102003820038200382003820038
100242003715008219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162419785010000102003820038200382003820038
1002420037150042619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162319785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uhadd v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150096119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150066119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150029706119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640416331978510000102003820038200382003820038
100242003715002706119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150048306119667251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
100242003715000053619687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150024306119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
100242003715001206119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150035106119687251001010100001010000502848066200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640316131978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uhadd v0.4s, v8.4s, v9.4s
  uhadd v1.4s, v8.4s, v9.4s
  uhadd v2.4s, v8.4s, v9.4s
  uhadd v3.4s, v8.4s, v9.4s
  uhadd v4.4s, v8.4s, v9.4s
  uhadd v5.4s, v8.4s, v9.4s
  uhadd v6.4s, v8.4s, v9.4s
  uhadd v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511031611200350800001002003920039200392003920039
802042003815000000032525801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200760800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815000001804025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038150000016506125801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150453925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000103502004164420035080000102003920039200392003920039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502004163520035080000102003920039200392003920039
8002420038150243925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502006164320035080000102003920039200392003920039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502006166420035080000102003920039200392003920039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502014163420035080000102003920039200392003920039
800242003815098125800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502003167620035080000102003920039200392003920039
80024200381505193925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502006163420035080000102003920039200392003920039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502006164720035080000102003920039200392003920039
80024200381504773925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502006164420035080000102003920039200392003920039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502004164720035080000102003920039200392003920039