Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UHADD (vector, 8H)

Test 1: uops

Code:

  uhadd v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
100420371508416872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715023916872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uhadd v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715011061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001002007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000961196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150004861196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000568196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000027101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000307101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000900611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
1002420037150001200611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uhadd v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150016619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371501572619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715096119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715036119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150156119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100207101161119791100001002003820038200382003820038
102042003715036119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640416221978510000102003820038200382003820038
10024200371500082196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640217221978510000102003820038200382003820038
100242003715001261196872510010101000010100005028476800200182003720037184453187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000277196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715002761196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000346196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uhadd v0.8h, v8.8h, v9.8h
  uhadd v1.8h, v8.8h, v9.8h
  uhadd v2.8h, v8.8h, v9.8h
  uhadd v3.8h, v8.8h, v9.8h
  uhadd v4.8h, v8.8h, v9.8h
  uhadd v5.8h, v8.8h, v9.8h
  uhadd v6.8h, v8.8h, v9.8h
  uhadd v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200671500000029258010810080008100800205006401321200192003820038997769989801202008003220016006420038200381180201100991001008000010000011151181160120035800001002003920039200392003920039
802042003815000060292580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100007811151180160020035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051101161120035800001002003920039200392003920039
802042003815000021040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051101161120035800001002003920039200392003920039
8020420038150001002712580100100800001008000050064000012001920038200389973610021801002008000020016000020038200381180201100991001008000010000000051101161120035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051101161220035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051101161120035800001002003920039200392003920039
802042003815000000130258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051101161120035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051101161120035800001002003920039200392003920039
80204200381500100040258010011680000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715000002292580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020716352003580000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020516652003580000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020516352003580000102003920039200392003920039
80024200381500006392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020516352003580000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020516552003580000102003920039200392003920039
80024200381500100392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020516352003580000102003920039200392003920039
800242003815000021392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020516352003580000102003920039200392003920039
800242003815000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100755020316352003580000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020517552003580000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020416552003580000102003920039200392003920039