Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UHSUB (vector, 2S)

Test 1: uops

Code:

  uhsub v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203716061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203716061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715961168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150156168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150251168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150156168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037151261168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uhsub v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500126119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150066119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197912100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071021611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820087200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150006619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715036119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715036119687251001010100121010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018201332008418444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820085
1002420037150053619687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715036119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150096419687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037156025119687251001010100001010000502847680120018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uhsub v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100137101161119791100001002003820038200382003820038
102042003714900611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100137101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001004637101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100104566422847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000187101162119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100137101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100037101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100037101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020090200372003718422318745101002001000020020000200372003711102011009910010010000100097101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150061196872510060101000010100005028476802001802003720037184440318767100102010000202000020037200371110021109101010000104410640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001802003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001802003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001802003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001802003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001802003720037184440318767100102010000202000020037200371110021109101010000100010640216221978510000102003820038200382003820038
1002420037149061196872510010101000010100005028476802001802003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768020018320037200371844403187671001020100002020000200372003711100211091010100001000543640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001802003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001802003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uhsub v0.2s, v8.2s, v9.2s
  uhsub v1.2s, v8.2s, v9.2s
  uhsub v2.2s, v8.2s, v9.2s
  uhsub v3.2s, v8.2s, v9.2s
  uhsub v4.2s, v8.2s, v9.2s
  uhsub v5.2s, v8.2s, v9.2s
  uhsub v6.2s, v8.2s, v9.2s
  uhsub v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420057150100040258010010080000100800005006400001200192003820038997303999680100200800002001600002003820038118020110099100100800001000000511031632200350800001002003920039200392003920039
8020420038150000040258010012480000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000100511021622200350800001002003920039200392003920039
8020420038150000040258010010080000100800005006400001200192003820038997373999680100200800002001600002003820038118020110099100100800001000200511021622200350800001002003920039200392003920039
8020420038150000040258010010080000100800005006400001200192003820038997303999680100200800002001600002003820038118020110099100100800001000000511021622200350800001002003920039200392003920039
8020420038150000040258010010080000100800005006400001200192003820038997303999680100200800002001600002003820038118020110099100100800001000300511021622200350800001002003920039200392003920039
8020420038150000040258010010080000100800005006400001200192003820038997303999680100200800002001600002003820038118020110099100100800001000060511021622200350800001002003920088200392003920039
8020420038150000040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000200511021622200350800001002003920039200392003920039
8020420038150000040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000000511021622200350800001002003920039200392003920039
8020420038150000040258010010080000100800005006400001200192003820038997303999680100200800002001600002003820038118020110099100100800001000100511021622200350800001002003920039200392003920039
8020420038150000040258010010080000100800005006400001200192003820038997303999680100200800002001600002003820038218020110099100100800001000000511021622200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500103925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039
80024200381500003925802001080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050050201161120035080000102003920039200392003920039
80024200381500006092580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010003854050201161120035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100040050201161120035080000102003920039200392003920039
800242003815000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000443050201161120035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899967100188001020800002016000020038200381180021109101080000100053050201161120035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100010050201161120035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039