Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UHSUB (vector, 8B)

Test 1: uops

Code:

  uhsub v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000373116111787100020382038203820382038
1004203715054716872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  uhsub v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
1020420037150000456119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500005376119687251010012510000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
1020420037150000366119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500004326119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500004986119676251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150361196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
100242003715036061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371501861196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
100242003715024156196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uhsub v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371502406119687251010010010000100100005002847680052001820037200371842231874510100200100002002000020037200371110201100991001001000010000710001161119791100001002003820038200382003820038
10204200371502406119687251010010010000100100005002847680052001820037200371842231874510100200100002002000020037200371110201100991001001000010000710511161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680102001820037200371842231874510100200100002002000020037200371110201100991001001000010000710511161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680052001820037200371842231874510100200100002002000020037200371110201100991001001000010000710001161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680052001820037200371842231874510100200100002002000020037200371110201100991001001000010000710001161119791100001002003820038200382003820038
1020420037150016119687251010010010000100100005002847680052001820037200371842231874510100200100002002000020037200371110201100991001001000010000710511161119791100001002003820038200382003820038
102042003715012012819687251010010010000100100005002847680052001820037200371842231874510100200100002002000020037200371110201100991001001000010000710001161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680052001820037200371842231874510100200100002002000020037200371110201100991001001000010000710001161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680002001820037200371842231874510100200100002002000020037200371110201100991001001000010000710511161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680002001820037200371842231874510100200100002002000020037200371110201100991001001000010000710001161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715072260719687251001010100001010000502850246120018200372003718444318767100102010000202000020037200842110021109101010000100006441324101019785010000102003820038200382003820085
10024200371503326219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006441016101019785010000102003820038200382003820038
1002420037149272500196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000064481610519785010000102003820038200382003820038
1002420037150122621968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000644516111119785010000102003820038200382003820038
1002420037150392621968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000644111651019785010000102003820038200382003820038
1002420037150026219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006441016111119785010000102003820038200382003820038
1002420037150026219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100906441016111019785010000102003820038200382003820038
10024200371504826219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006448168819785010000102003820038200382003820038
10024200371500262196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000064410168819785010000102003820038200382003820038
1002420037150026219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006441016101019785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uhsub v0.8b, v8.8b, v9.8b
  uhsub v1.8b, v8.8b, v9.8b
  uhsub v2.8b, v8.8b, v9.8b
  uhsub v3.8b, v8.8b, v9.8b
  uhsub v4.8b, v8.8b, v9.8b
  uhsub v5.8b, v8.8b, v9.8b
  uhsub v6.8b, v8.8b, v9.8b
  uhsub v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015104525801001008000010080000500640000120019020038200389973399968010020080000200160000200382003811802011009910010080000100051102161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019020038200389973399968010020080000200160000200382003811802011009910010080000100251101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150154025801001008000010080000500640000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150214025801001008000010080000500640000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019020038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309l2 tlb miss instruction (0a)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715000120392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000050200151611112003580000102003920039200392003920039
80024200381500000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000050200111611122003580000102003920039200902003920039
800242003815000003925800101080000108000050640000012001920038200389996310018800102080036201600002003820038118002110910108000010000502009168132003580000102003920039200392003920039
80024200381500200392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000050200121612102003580000102003920039200392003920039
80024200381500100392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000050200141610102003580000102003920039200392003920039
80024200381500100392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000050200121611122003580000102003920039200392003920039
8002420038150020039258001010800001080000506400000120019200382003899963100188001020800002016000020038200381180021109101080000100005020010161272003580000102003920039200392003920039
8002420038150030039258001010800001080000506400000120019200382003899963100188001020800002016000020038200381180021109101080000100005020011167112003580000102003920039200392003920039
8002420038150020039258001010800001080000506400000120019200382003899963100188001020800002016000020038200381180021109101080000100005020091611112003580000102003920039200392003920039
800242003815002003925800101080000108000050640000112001920038200389996310018800102080000201600002003820038118002110910108000010000502007167112003580000102003920039200392003920039