Firestorm: UMAXV (vector, 4H) measurements

Code:

  umaxv h0, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	0	0	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	2	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	0	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	0	103	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	0	191	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	0	0	0	0	84	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1148	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	0	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3086
1004	3037	23	0	0	0	0	0	0	0	61	2547	25	1000	1000	1000	398160	3018	3037	3037	2414	6	2895	1150	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  umaxv h0, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	1	0	0	0	0	0	1041	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	3	2	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	3	0	710	2	16	2	2	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4281216	30018	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	1367	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	19	6	710	2	16	2	2	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29633	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	9	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30076	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	6	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	1	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30074	30038
10024	30037	224	0	0	0	1068	704	0	5243	29547	152	10069	13	10056	11	11050	71	4286624	1	30306	30415	30370	28300	35	28915	11216	26	11313	24	22648	30415	30037	9	1	10021	10	9	10	10	10000	10	0	0	0	0	1	25210	4	832	2	89	3	3	29926	3	0	10000	10	30413	30133	30415	30416	30422
10024	30404	228	0	9	9	1068	792	0	5822	29493	189	10079	14	10072	15	10243	87	4287976	1	30310	30453	30463	28321	37	28936	11214	20	11402	26	22942	30417	30453	9	1	10021	10	9	10	10	10000	10	2	0	0	0	0	25248	0	850	3	88	5	2	29917	3	0	10000	10	30320	30455	30463	30420	30369
10024	30415	228	0	9	9	1191	792	1	5890	29475	172	10087	12	10064	13	11350	50	4287976	0	30306	30451	30464	28318	6	28917	11344	26	10000	24	22970	30463	30414	9	1	10021	10	9	10	10	10000	10	4	0	0	0	0	13870	2	829	3	89	3	4	29972	4	0	10000	10	30133	30370	30181	30278	30085

Test 3: throughput

Count: 8

Code:

  umaxv h0, v8.4h
  umaxv h1, v8.4h
  umaxv h2, v8.4h
  umaxv h3, v8.4h
  umaxv h4, v8.4h
  umaxv h5, v8.4h
  umaxv h6, v8.4h
  umaxv h7, v8.4h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20039	150	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	0	16	0	0	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	410	25	80108	100	80008	100	80020	500	640132	1	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	0	16	0	0	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	1	16	0	0	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	1	16	0	0	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20090	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	0	16	0	0	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	0	16	0	0	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	0	16	0	0	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	1	16	0	0	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	30	25	80207	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	1	16	0	0	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	1	16	0	0	20036	80000	100	20040	20040	20040	20040	20040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20051	150	0	0	0	0	0	0	0	0	147	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20142	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	0	0	1	16	0	0	1	1	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	0	0	1	16	0	0	1	1	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	61	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	0	0	1	16	0	0	1	1	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	0	0	1	16	0	0	1	1	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	0	0	1	16	0	0	1	1	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	0	0	1	16	0	0	1	1	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	0	0	1	16	0	0	1	1	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	103	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	0	0	1	16	0	0	1	1	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	0	0	1	16	0	0	1	1	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	0	0	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	0	0	1	16	0	0	1	1	20036	0	80000	10	20040	20040	20040	20040	20040

UMAXV (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations