Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

UMAXV (vector, 4S)

Test 1: uops

Code:

  umaxv s0, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)0308191e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
10043037220006125472510001000100039816013018303730372414328951000100020003037303711100110000073216112629100030383038303830383038
10043037230008225472510001000100039816013018303730372414328951000100020003037303711100110001073116112629100030383038303830383038
10043037220006125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037220006125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037220006125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
100430372300312425472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037220006125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037220006125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037220006125472510001000100039816003018303730372414328951000100020003037303711100110000073116112661100030383038303830383038
10043037220006125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  umaxv s0, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)03071e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a8acc2cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372250006129547251010010010000100100005004277160300183003730037282643287451010021210000200200003003730037111020110099100100100001000000071021622296330100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071021622296330100001003003830038300383003830038
102043003722500072629547251010010010000100100005004277160300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071021622296330100001003003830038300383003830038
102043003722500075929547251010010010000100100005004277160300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071021622296330100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071021622296330100001003003830085300383003830038
10204300372250006129547251010010010000100100005004277160300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071021622296330100001003003830038300383003830038
102043003722503606129547251010010010000100100005004277160300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071021622296330100001003003830038300383003830038
1020430037225051606129547251010010010000100100005004277160300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071021622296330100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071021622296330100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160300183003730037282643287451010020010000200200003003730037111020110099100100100001000000071021622296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)031e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a8acc5cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024300372250747295474410010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300183003730037282860328767104602010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722554661295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100130640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037224061295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300183003730037282860328767103102010168202000030037300371110021109101010000100000640216232962910000103003830038300383003830038
10024300372250536295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250726295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722557061295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  umaxv s0, v8.4s
  umaxv s1, v8.4s
  umaxv s2, v8.4s
  umaxv s3, v8.4s
  umaxv s4, v8.4s
  umaxv s5, v8.4s
  umaxv s6, v8.4s
  umaxv s7, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9facc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
8020420058150354302580108100800081008002050064013220069020039200399977699908012020080032200160064200392003911802011009910010080000100011151180160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013220020020039200399977699908012020080032200160064200392003911802011009910010080000100011151180160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013220020020039200399977699908012020080032200160064200392003911802011009910010080000100011151180160020036800001002004020040200402004020040
802042003915006952580108100800081008002050064013220020020039200399977699908012020080032200160064200392003911802011009910010080000100011151180160020036800001002004020040200402004020040
8020420039150231302580108100800081008002050064013220020020039200399977699908012020080032200160064200392003911802011009910010080000100011151180160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013220020020039200399977699908012020080032200160064200392003911802011009910010080000100011151180160020036800001002004020040200402004020040
8020420039150291302580108100800081008002050064013220020020039200399977699908012020080032200160064200392003911802011009910010080000100011151180160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013220020020039200399977699908012020080032200160064200392003911802011009910010080000100011151180160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013220020020039200399977699908012020080032200160064200392003911802011009910010080000100011151180160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013220020020039201029977699908012020080032200160064200392003911802011009910010080000100011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)03090b181e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8cfd5d6ddinst fetch restart (de)e0ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
800242003915000018325258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010050207167620036080000102004020040200402004020040
80024200391500000103258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010050206166420036080000102004020040200402004020040
80024200391500001840258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010050203166420036080000102004020040200402004020040
80024200391500001840258001010800001080000506400002002020039200399996310019800102080000201600002004120039118002110910108000010050207166620036080000102004020040200402004020040
8002420039150010246402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100502041664200362480000102004020040200402004020040
8002420039150000640258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010050204165820036080000102004020040200402004020040
800242003915000040540258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010050203163520036080000102004020040200402004020040
80024200391500001240258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010050204166620036080000102004020040200402004020040
8002420039150000040258001010800001080000506400002014320039200399996310019800102080000201600002003920039118002110910108000010050204163420036080000102004020040200402004020040
8002420039150000040258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010150204164320036080000102004020040200402004020040