Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMAX (vector, 4S)

Test 1: uops

Code:

  umax v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000115226468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715014916872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371508316872510001000100026468012018203720371572318951000100020002037203711100110008073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  umax v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715002061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000631196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000251196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010063640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010121000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001039640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001003640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001033640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000104215640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001020640216221985210000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001016640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  umax v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000300611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715001000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100000710116111979125100001002003820038200382003820038
102042003715000000611968725101001001000012510000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010010071021611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000135071011611197910100001002003820038200382003820038
102042003715000000611968744101001001000010010000500284768020018200372003718422031876210100200100002002000020037200371110201100991001001000010000071031711197910100001002003820038200382003820038
102042003715000010806119687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100015071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768020018200372003718422031874410125200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011621197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150001031968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010240320640216221978510000102003820086200382003820038
100242008615510615196872510010101001214100005528476801200182008420037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000103196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000900640216221978510000102003820038200382003820038
10024200371500082196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000600640216221978510000102003820038200382003820038
100242003714902761196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000300640216221978510000102003820038200382003820038
10024200371500061196872510022101000011100005028476801200182013420037184443187671001020100002020000200372003711100211091010100001020000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001020300640216221978510000102008520038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000251196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010002700640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  umax v0.4s, v8.4s, v9.4s
  umax v1.4s, v8.4s, v9.4s
  umax v2.4s, v8.4s, v9.4s
  umax v3.4s, v8.4s, v9.4s
  umax v4.4s, v8.4s, v9.4s
  umax v5.4s, v8.4s, v9.4s
  umax v6.4s, v8.4s, v9.4s
  umax v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005715004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000002511031611200350800001002003920039200392003920039
80204200381500402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000310180511011611200350800001002003920039200392003920039
8020420088150184025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000001290511011611200350800001002003920039200392003920039
8020420038150021125801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640756020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000030511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000100502016160862003580000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000502081606122003580000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000502012160862003580000102003920039200392003920039
8002420038150039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000050208160882003580000102003920039200392003920039
8002420038150039258001010800801080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000050206160682003580000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000300502061606122003580000102003920039200392003920039
800242003815005142580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000502012160862003580000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000502081606122003580000102003920039200392003920039
8002420038150039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000050206160682003580000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000183050208160882003580000102003920039200392003920039