Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMINP (vector, 4S)

Test 1: uops

Code:

  uminp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716000061168725100010001000264680120182037203715723189510001000200020372037111001100020073116111787100020382038203820382038
1004203715000061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037150000124168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715000661168725100010001000264680120182037203715723189510001000200020372037111001100010073116111787100020382038203820382038
1004203715000061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715000061168725100010001000264680120182037203715723189510001000200020372037111001100003073116111787100020382038203820382038
1004203715000061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715000061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715000061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715001061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uminp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715002101968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000017101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820085200382003820038
102042003715001071968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000307101161119857100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010020007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371490611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000640516671978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000640616671978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000640616551978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000640716771978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000640616661978510000102003820038200382003820038
100242003715001931968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000640616661978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000640616661978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000640616661978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640716771978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000640616761978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uminp v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500006619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100001071011611197910100001002003820038200382003820038
10204200371500150881031968725101001001000010010000500284768012001820037200371842231876210100202100002002000020037200371110201100991001001000010000024371011611197910100001002003820038200382003820038
10204200371500306119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071022411197910100001002003820038200382003820038
1020420037150012012419687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000010319687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011612198630100001002003820134200382003820038
102042003715002408219676251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000010319687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000072619687251010010010000100100005002847680120018200372003718422318745102722001000020020000200372003711102011009910010010000100000371011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100212071021611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715008219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640316331991310000102003820038200382003820038
100242003715008419687251001010100001010000502847680020018200832003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uminp v0.4s, v8.4s, v9.4s
  uminp v1.4s, v8.4s, v9.4s
  uminp v2.4s, v8.4s, v9.4s
  uminp v3.4s, v8.4s, v9.4s
  uminp v4.4s, v8.4s, v9.4s
  uminp v5.4s, v8.4s, v9.4s
  uminp v6.4s, v8.4s, v9.4s
  uminp v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001001051105162120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd2l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500392580010108000010800005064000012001920038200389996031001880010208000020160000200382003811800211091010800001000502060416442003580000102003920039200392003920039
80024200381490392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000502060416342003580000102003920039200392003920039
800242003815007042580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000502060316342003580000102003920039200392003920039
80024200381500392580010108000010800005064000012001920038200389996031001880010208000020160000200382003811800211091010800001000502060316442011080000102003920039200392003920039
80024200381500392580010108000010800995064000002001920038200389996031001880010208000020160000200382003811800211091010800001000502080416342003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000502070416432003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000502070416432003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000502070416432003580000102003920039200392003920039
80024200381500602580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000502070416342003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000502080416432003580000102003920039200392003920039