Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMINV (vector, 8H)

Test 1: uops

Code:

  uminv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03091e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230006125472510001000100039816013018303730372414328951000100020003037303711100110000073216112629100030383038303830383038
10043037220006125472510001000100039816003018303730372414328951000100020003037303711100110000373116112629100030383038303830383038
10043037220006125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
100430372300033025472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037220006125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037230006125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
100430372200045125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037230006125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
100430372200061254725100010001000398160130183037303724143289510001000200030373037111001100001873116112629100030383038303830383038
100430372200050925472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  uminv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722501662954725101001001000010010000500427716003001830037300372826432874510100200100002002000030037300371110201100991001001000010000000710021611296330100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716013001830037300372826432874510100200100002002000030037300371110201100991001001000010000104710011611296330100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716013001830037300372826432874510100200100002002000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001830037300372826432874510100200100002002000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
102043003722532352954725101001001000010010000500427716013001830037300372826432874510100200100002002000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716013001830037300372826432874510100200100002002000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
10204300372240612954725101001001000010010000500427716013001830037300372826432874510100200100002002000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
10204300372250612954725101271001000010010000500427716013001830037300372826432874510100200100002002000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
10204300372240612954725101001001000010010000500427716003001830037300372826432874510100200100002002000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716013001830037300372826432874510100200100002002000030037300371110201100991001001000010000000710011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000640416222962910000103003830038300383003830038
1002430037225000006129547251001010100001010000504277160030018300373003728286328767100102010000202000030083300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225000006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100330640216222962910000103003830038300383003830038
10024300372250100078929547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225000006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225000006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225000006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100030640216222962910000103003830038300383003830038
1002430037225000006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250000072629547251001010100001010000504277160030018300843003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250000072629547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  uminv h0, v8.8h
  uminv h1, v8.8h
  uminv h2, v8.8h
  uminv h3, v8.8h
  uminv h4, v8.8h
  uminv h5, v8.8h
  uminv h6, v8.8h
  uminv h7, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391501130258010810080008100800205006401321200202003920039997769990801202008003220016006420039200391180201100991001008000010000011151182161120036800001002004020040200402004020040
80204200391501130258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010002311151181161120036800001002004020040200402004020040
80204200391501130258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391501130258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010001011151181481120036800001002004020040200402004020040
80204200391501130258010810080008100800205006409640200202003920039997769990801202008003220016006420039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391501130258010810080008100800205006401321200202003920039997769990801202008003220016006420039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
802042003915011695258010810080008100800205006401321200202003920039997769990801202008003220016006420039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391501130258010810080008100800205006401321200202003920039997769990801202008003220016006420039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391501130258010810080008100800205006401321200202003920039997769990801202008003220016006420039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391501130258010810080008100800205006401320200202003920039997769990801202008003220016006420039200391180201100991001008000010000011151181161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd2d5map dispatch bubble (d6)ddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100350200416242003672080000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100050200216242003658080000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100050200416422003658080000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100050450416422003658080000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100050200216242003658080000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100050200416442003658080000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100050200416422003658080000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100050200216442003658080000102004020040200402004020040
800242003915007052580010108000010800005064000020020200392003999963100198001020800002016000020088200391180021109101080000101050200216442003658080000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100050200416432003658080000102004020040200402004020040