Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMIN (vector, 16B)

Test 1: uops

Code:

  umin v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100002773216111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715015616872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  umin v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101261119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968725100231110012101000050284768012001820037200371844731876710010201000020203382003720037111002110910101000010006602162119785010000102003820038200382003820038
10024200371500611968725100241410000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010106402162219785010000102003820038200382003820038
100242003715021611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162319785210000102003820038200382003820038
100242003715031031968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715002531968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010106402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  umin v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000710116111979100100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000710116111979100100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000710116111979100100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000710116111979100100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000710116111979100100001002003820038200382003820038
102042003715000034619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100240710116111979100100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000710116111979100100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000710116111979120100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000710116111979100100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010010710116111979100100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000040919687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000012906402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000009419687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010050006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001410000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000012906402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200852003820038
10024200371500000006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000007119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  umin v0.16b, v8.16b, v9.16b
  umin v1.16b, v8.16b, v9.16b
  umin v2.16b, v8.16b, v9.16b
  umin v3.16b, v8.16b, v9.16b
  umin v4.16b, v8.16b, v9.16b
  umin v5.16b, v8.16b, v9.16b
  umin v6.16b, v8.16b, v9.16b
  umin v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100200247051102161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000001051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038150001240258010010080000100800005006400001200192010220038997339996801002008000020216000020038200871180201100991001008000010000001251451421120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000351101161120035800001002003920039200392003920039
80204200381500008225801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000001351101161120035800001002003920039200392003920039
80204200381500008225801001008000010080000500640000020022200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500306125801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815090392580010108009310800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000250201161120035080000102003920039200392003920039
800242003815000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201161120035080000102003920039200392003920039
800242003815000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201161120035080000102003920039200392003920039
800242003815000392580010108000010800005064000002001920038200389996310018800102080000201600002008620038118002110910108000010009050201161120035080000102003920039200392003920039
800242003815000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201161120035080000102003920039200392003920187
800242003815000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000050381161120035080000102003920039200392003920039
800242003814900392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201161120035080000102003920039200392003920039
8002420038150001022580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201161120035080000102003920039200392003920039
800242003815000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201161120035080000102003920039200392003920039
800242003815000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201161120035080000102003920039200392003920039