Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMIN (vector, 4S)

Test 1: uops

Code:

  umin v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371508216872510001000100026468012018203720371572318951000100020002037203711100110000073416111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037161776116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371566116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715010316872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  umin v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715010005991968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100071021622197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100071021622197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100071021622197910100001002003820038200382003820038
10204200371500003611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100071021622197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100071021622197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100071021622197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422318745101002001000020220000200372003711102011009910010010000100071021622197910100001002003820038200382003820038
1020420037150000011141968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100071021622197910100001002003820038200382003820038
102042003715000001031968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100171021622197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150025619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316221978510000102003820038200382003820038
1002420037150082119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150010519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150042519687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715008219687251001011100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715008219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  umin v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000147196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007102161119791100001002003820038200382003820038
1020420037150000103196762510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000207101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000500196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000965196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000385196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000084196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000124196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000170196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020210099100100100001000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150110008219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100046632162219785210000102003820038200382003820086
1002420037150000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500001208419687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000021014719687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100201806402163319785010000102003820038200382003820038
10024200371500019886119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500001206119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000012419687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402163419785010000102003820038200382003820038
1002420037152000006119687251002412100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  umin v0.4s, v8.4s, v9.4s
  umin v1.4s, v8.4s, v9.4s
  umin v2.4s, v8.4s, v9.4s
  umin v3.4s, v8.4s, v9.4s
  umin v4.4s, v8.4s, v9.4s
  umin v5.4s, v8.4s, v9.4s
  umin v6.4s, v8.4s, v9.4s
  umin v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051102161120035800001002003920039200392003920039
802042003815012402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150174402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008009550064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815030402580100100800001008000050064000012001920038200389973399968010020080136200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051291161120035800001002003920039200392003920039
80204200381500405080100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100251101161120035800001002003920039200392003920039
8020420038150910232580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)dadbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500392580010108000010800005064000001200190200382003899963100188001020800002016000020038200381180021109101080000105020000121600452003580000102003920039200392003920039
80024200381500392580010108000010800005064000001200190200382003899963100188001020800002016000020038200381180021109101080000105020000101600742003580000102003920039200392003920039
800242003814966092580010108000010800005064000000200190200382003899963100188001020800002016000020038200381180021109101080000105020000616001272003580000102003920039200392003920039
8002420038150039258001010800001080000506400000020019020038200389996310018800102080000201600002003820038118002110910108000010502000061600572003580000102003920039200392008920039
8002420038150039258001010800001080000506400000020019020038200389996310018800102080000201600002003820038118002110910108000010502031171600542003580000102003920039200392003920039
8002420038150039258001010800001080000506400000020019020038200389996310018800102080000201600002003820038118002110910108000010502000051601352003580000102003920039200882003920039
800242003815021392580010108000010800005064000001200190200382003899963100188001020800002016000020038200381180021109101080000105020000616001272003580000102003920039200392003920039
800242003815021392580010108000010800005064000000200190200382003899963100188001020800002016000020038200381180021109101080000105020000616005102003580000102003920039200392003920039
80024200381500392580010108000010800005064000000200190200382003899963100188001020800002016000020038200381180021109101080000105020000516006122003580000102003920039200392003920039
8002420038150039258001010800921080000506400000020019020038200389996310018800102080000201600002003820038118002110910108000010502000051600592003580000102003920039200392003920039