Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMIN (vector, 8B)

Test 1: uops

Code:

  umin v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)a9acc3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
1004203715306116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  umin v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150218219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102052003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715036119687251010010010000100100005002847680020018200372003718422318818101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150053619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020091200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371502761196872510010101000010100005028476802012620037200371844431876710010201000020200002003720037111002110910101000010000640716221978510000102003820085200382003820038
1002420037150061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500103196872510010101000010100005028476802001820037200371845131876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150361196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820083
1002420037150061196872510010101000010100005028476802001820084200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037156061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002520037150061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  umin v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371490061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
1020420037150036361196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715002182196872510100102100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500006619687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001013640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001010640216231978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001013640216221978510000102003820038200382003820038
10024200371490006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
10024200371500006119687251001010100001210000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640316221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  umin v0.8b, v8.8b, v9.8b
  umin v1.8b, v8.8b, v9.8b
  umin v2.8b, v8.8b, v9.8b
  umin v3.8b, v8.8b, v9.8b
  umin v4.8b, v8.8b, v9.8b
  umin v5.8b, v8.8b, v9.8b
  umin v6.8b, v8.8b, v9.8b
  umin v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200481500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010013051104161120035800001002003920039200392003920039
802042003815000515258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040628010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010016051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010013051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010020051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010023051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420059150000000000392580012108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010001060502004162320035080000102003920086200392003920039
8002420038150000000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000502001161120035080000102003920039200392003920039
80024200381500000000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100033000502001161120035080000102003920039200392003920039
8002420038150100000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000502001161120084080000102003920039200392003920039
8002420038150000000000392580012128000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000000502001161120035080000102003920039200392003920039
80024200381500000000004425800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100021060502001161120035080000102003920039200392003920039
8002420038150000000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000502201161120035080000102003920039200392003920039
8002420038150000000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000502001161120035080000102003920039200392003920039
8002420038150000000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000502001161120035080000102003920039200392003920039
8002420038150000000000392580294108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010001000502001161120035080000102003920039200392003920039