Firestorm: UMLAL (by element, 2D) measurements

Code:

  umlal v0.2d, v1.2s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	1	1	0	1	64	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	75	8	16	5	5	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	1	1	0	1	64	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	75	5	16	5	5	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	1	1	0	1	64	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	75	5	16	6	6	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	1	1	0	1	64	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	75	5	16	5	5	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	1	1	0	1	64	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	75	5	16	6	6	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	1	1	0	1	64	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	75	5	16	7	6	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	1	1	0	1	64	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	6	75	5	16	5	5	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	1	1	0	1	64	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	75	5	16	6	6	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	1	1	12	2	64	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	75	5	16	6	6	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	1	1	0	1	64	2548	25	1000	1000	1000	398313	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	75	5	16	5	5	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  umlal v0.2d, v1.2s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28272	6	28741	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	1	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	0	0	710	0	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	12	0	830	29548	25	10100	100	10000	100	10000	500	4278670	0	30018	30037	30037	28269	3	28763	10100	204	10000	206	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	12	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4278157	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	150	0	0	0	710	0	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	168	0	0	0	710	0	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	18	2	640	2	16	2	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	147	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10020	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	120	0	640	2	16	2	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	144	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	82	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	87	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	6	18	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	138	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	138	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	150	0	640	2	16	2	3	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  umlal v0.2d, v0.2s, v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	21	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	9	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	48	3	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	54	3	739	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10596	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	53	3	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	42	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	68	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	38	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	5	6	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	42	3	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	43	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	1	1	0	0	0	0	2	71	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	46	18	644	10	16	5	11	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	1	1	0	0	0	0	2	71	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	47	0	644	5	16	12	12	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	0	0	0	2	71	29548	25	10010	10	10000	14	10000	50	4280027	0	30018	30037	30037	28287	3	28767	10161	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	48	12	644	10	16	5	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	0	0	0	2	71	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	47	24	644	10	16	8	8	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	0	0	0	2	71	29548	44	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	48	9	644	10	16	10	5	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	0	0	0	2	71	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	50	0	644	11	16	10	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	0	0	0	2	71	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	50	0	644	10	16	10	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	0	0	0	2	71	29548	25	10010	10	10000	10	10149	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	2	1	10021	10	9	10	10	10000	10	53	0	644	10	16	10	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	0	0	0	2	71	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	6	3	644	10	16	12	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	0	0	0	2	71	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	43	0	644	10	16	10	10	29630	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  umlal v0.2d, v1.2s, v0.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	164	124	29548	25	10100	100	10008	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	20	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	214	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	1000	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	995	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	132	363	29548	25	10100	100	10000	100	10000	500	4277313	1	30066	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	409	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	785	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	895	29548	25	10115	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	117	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	3	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	150	726	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	631	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	726	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10017	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10025	30037	225	0	61	29548	25	10010	12	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  umlal v0.2d, v8.2s, v9.s[1]
  movi v1.16b, 0
  umlal v1.2d, v8.2s, v9.s[1]
  movi v2.16b, 0
  umlal v2.2d, v8.2s, v9.s[1]
  movi v3.16b, 0
  umlal v3.2d, v8.2s, v9.s[1]
  movi v4.16b, 0
  umlal v4.2d, v8.2s, v9.s[1]
  movi v5.16b, 0
  umlal v5.2d, v8.2s, v9.s[1]
  movi v6.16b, 0
  umlal v6.2d, v8.2s, v9.s[1]
  movi v7.16b, 0
  umlal v7.2d, v8.2s, v9.s[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	150	0	0	60	25	80100	100	80000	100	80000	500	640000	0	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10112	0	0	0	1	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	1	0	4	16	2	3	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	0	20122	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	0	0	3	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	4	0	0	0	10111	5	1	0	3	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	0	0	0	4	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	123	25	80100	100	80000	100	80000	500	640000	0	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	2	0	0	0	0	0	0	10111	0	0	0	3	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	39	25	80100	100	80000	100	80000	500	640000	1	1	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	1	0	5	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	0	0	0	4	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	39	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	0	0	0	4	16	1	1	20061	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	39	25	80100	100	80000	100	80000	500	640000	0	1	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10111	5	0	0	3	16	1	1	20061	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20064	150	0	0	0	0	0	337	25	80012	12	80000	12	80000	62	640000	1	1	20031	20046	20050	0	3	22	80012	20	80000	20	240000	20048	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10045	6	2	2	0	19	22	2	34	2	17	21	20049	2	30	0	160000	10	20047	20051	20047	20053	20049
160024	20046	150	0	0	0	0	0	87	25	80012	12	80000	12	80000	62	640000	1	1	20029	20148	20046	0	3	22	80012	20	80000	20	240000	20053	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10047	6	2	2	0	20	24	4	37	2	20	21	20043	2	16	0	160000	10	20047	20047	20047	20047	20047
160024	20050	150	0	0	0	0	0	72	25	80012	12	80000	12	80000	62	640000	0	1	20031	20052	20052	0	34	22	80012	20	80000	20	240000	20046	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10044	3	1	1	0	22	22	2	31	4	18	17	20045	2	16	0	160000	10	20212	20053	20047	20049	20049
160024	20052	150	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	0	0	20027	20046	20050	0	3	22	80012	20	80000	20	240000	20048	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	2	6	10040	6	1	2	0	16	20	1	33	4	20	19	20043	2	31	0	160000	10	20051	20049	20049	20047	20049
160024	20050	151	0	0	0	0	0	51	25	80012	12	80000	12	80000	62	640000	1	0	20031	20048	20048	0	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	2	0	2	0	0	10041	3	1	1	0	18	20	2	32	2	16	19	20043	2	15	0	160000	10	20049	20049	20049	20047	20047
160024	20050	156	0	0	0	0	0	194	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	0	3	22	80012	20	80000	20	240000	20046	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10037	3	1	1	0	19	24	1	32	2	18	22	20043	2	30	0	160000	10	20047	20047	20049	20049	20047
160024	20048	150	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	0	20029	20208	20046	0	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	2	0	0	0	0	0	10044	3	1	1	0	18	20	2	32	2	11	18	20043	2	15	0	160000	10	20047	20372	20049	20049	20047
160024	20046	150	0	0	0	0	0	66	25	80012	12	80000	12	80000	62	640000	1	0	20027	20048	20048	0	3	22	80012	20	80000	20	240000	20048	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10041	3	1	1	0	19	22	2	30	2	17	16	20045	2	15	0	160000	10	20049	20049	20047	20047	20049
160024	20046	150	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20048	0	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10037	3	1	1	0	17	20	1	32	2	18	18	20043	2	16	0	160000	10	20049	20049	20047	20047	20047
160024	20046	150	0	0	0	0	0	45	25	80012	12	80000	12	80000	62	640000	1	0	20029	20046	20046	0	3	22	80012	20	80000	20	240000	20046	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10040	3	1	1	0	18	22	2	32	2	16	18	20043	2	15	0	160000	10	20047	20047	20047	20047	20047

Test 6: throughput

Count: 12

Code:

  umlal v0.2d, v12.2s, v13.s[1]
  umlal v1.2d, v12.2s, v13.s[1]
  umlal v2.2d, v12.2s, v13.s[1]
  umlal v3.2d, v12.2s, v13.s[1]
  umlal v4.2d, v12.2s, v13.s[1]
  umlal v5.2d, v12.2s, v13.s[1]
  umlal v6.2d, v12.2s, v13.s[1]
  umlal v7.2d, v12.2s, v13.s[1]
  umlal v8.2d, v12.2s, v13.s[1]
  umlal v9.2d, v12.2s, v13.s[1]
  umlal v10.2d, v12.2s, v13.s[1]
  umlal v11.2d, v12.2s, v13.s[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2646

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	30922	225	0	0	0	41	0	25	120100	100	120000	100	120000	500	990000	1	31729	31748	30039	14973	3	14997	120100	200	120000	200	360000	30039	31748	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	31749	30040	31749	30040	31749
120204	30039	237	0	0	18	44	0	25	120100	100	120000	100	120000	500	990000	0	30021	30039	31748	16653	3	16706	120100	200	120000	200	360000	30039	31748	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	31749	30040	31749	30040	31749
120204	31748	225	0	0	0	61	0	25	120118	100	120018	100	120000	500	960000	0	30020	31748	30039	14973	3	14997	120100	200	120000	200	360000	30039	30040	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	31749	30040	31749	31749	30040
120204	30039	225	0	0	18	61	0	25	120100	100	120000	100	120000	500	4399524	0	30020	30039	31748	16653	3	16706	120100	200	120000	200	360000	30039	30040	1	1	120201	100	99	100	100	120000	100	0	0	0	3	7610	1	64	1	1	30036	0	120000	100	30041	30040	31749	30040	31749
120204	31748	225	0	0	1	41	6713	25	120100	100	120000	100	120000	500	960000	0	30020	30039	30039	14973	3	14997	120100	200	120000	200	360000	30039	30040	1	1	120201	100	99	100	100	120000	100	0	0	8	0	7610	1	16	1	1	31745	0	120000	100	30040	31749	30040	31749	30040
120204	30039	238	0	0	0	41	6713	25	120101	100	120018	100	120000	500	960000	0	30020	30039	31748	14973	3	14998	120100	200	120000	200	360000	31748	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	31749	30040	31749	30040	31749
120204	31748	225	0	0	0	42	0	25	120100	100	120000	100	120000	500	960000	0	31729	31748	30039	14973	3	14997	120100	200	120000	200	360000	30039	31748	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	31745	0	120000	100	31749	30040	31749	30040	31749
120204	31748	225	0	0	18	41	0	25	120118	100	120018	100	120000	500	960000	1	30020	30039	31748	16653	3	16706	120100	200	120000	200	360000	31748	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	30036	0	120000	100	31749	30040	31749	30040	31749
120204	31748	224	0	0	0	61	6713	25	120117	100	120000	100	120000	500	4399524	1	30021	31748	30039	14973	3	14997	120100	200	120000	200	360000	31748	30039	1	1	120201	100	99	100	100	120000	100	0	0	2	0	7610	1	16	1	1	30037	23	120000	100	30040	30040	30040	30040	30040
120204	31748	225	1	0	0	41	0	25	120100	100	120000	100	120000	500	990000	0	30020	30039	30039	14973	3	16706	120100	200	120000	200	360000	31748	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	2	1	30036	0	120000	100	30040	30040	30040	30040	30040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	31750	225	0	0	1	0	0	0	0	79	0	25	120010	10	120001	10	120000	50	990000	1	1	31729	30039	30039	15879	3	15019	120010	20	120000	20	360000	30922	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	18	2	0	28	16	1	1	1	19	27	30919	21	7	120000	10	31751	30041	30040	30040	30040
120024	30039	225	0	1	1	0	0	0	1	58	0	25	120027	10	120017	10	120000	50	960000	1	1	30021	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	15	4	0	24	16	1	1	1	19	26	30036	21	7	120000	10	30040	30040	30040	30923	30040
120024	30039	225	0	1	1	0	0	0	0	46	0	25	120010	10	120000	10	120000	50	990000	1	1	31729	30039	30039	15850	3	15019	120010	20	120000	20	360000	30039	31748	1	1	120021	10	9	10	10	120000	10	0	0	0	7524	3	13	3	0	26	16	1	1	1	25	28	30036	21	7	120000	10	31751	30041	31751	31751	30041
120024	30039	232	0	1	1	1	0	0	0	58	0	25	120010	10	120000	10	120000	50	960000	1	1	30020	30922	30039	14996	3	15019	120010	20	120000	20	360000	30040	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7524	3	14	4	0	25	16	1	1	1	24	26	30037	21	7	120000	10	30923	30040	30040	30040	30040
120024	30922	225	0	1	1	0	0	17	1	65	0	25	120010	10	120000	10	120000	60	960000	1	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30922	1	1	120021	10	9	10	10	120000	10	0	0	0	7524	3	13	3	0	24	16	1	1	1	26	26	30036	21	13	120000	10	30040	30040	30040	30923	30040
120024	30040	225	0	1	1	0	0	17	0	59	0	25	120011	10	120001	10	120000	50	990000	1	1	30021	30039	30922	14996	3	15020	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7524	3	13	2	0	15	16	1	1	1	28	25	30036	21	9	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	1	1	0	0	0	1	712	3405	25	120010	10	120000	10	120000	50	960000	1	1	30903	30039	30039	14996	3	15019	120010	20	120000	20	360000	30040	30040	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	13	3	0	22	16	1	1	1	27	17	31745	21	7	120000	10	30041	30041	30040	30040	30041
120024	30040	225	0	1	1	0	0	0	1	47	0	25	120027	10	120000	10	120000	50	990000	1	1	30021	30039	30039	14996	3	15019	120010	20	120000	20	360000	30922	31750	1	1	120021	10	9	10	10	120000	10	0	21	0	7522	3	18	2	0	26	57	1	1	1	27	20	30037	21	7	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	0	1	0	0	1	1	47	0	25	120011	10	120000	10	120000	50	990000	1	1	30020	30922	30040	14996	3	15020	120010	20	120000	20	360000	30039	30951	1	1	120021	10	9	10	10	120000	10	0	0	0	7524	3	13	4	0	26	16	1	1	1	28	16	30036	21	7	120000	10	30041	30041	30041	30041	30041
120024	30040	225	0	1	1	0	0	0	1	46	0	25	120010	10	120000	10	120000	50	990000	1	1	30903	30039	30922	14996	3	15019	120010	20	120000	20	360000	30922	30040	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	13	2	0	26	16	1	1	1	26	23	30036	21	7	120000	10	30040	30040	30041	30040	30040

UMLAL (by element, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations