Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMLAL (vector, 4S)

Test 1: uops

Code:

  umlal v0.4s, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303723786125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372308525482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100034893037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  umlal v0.4s, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500360612954825101001001000010010000500427731303001830228300372826532874510100200100002003000030037300371110201100991001001000010000071003162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427867003001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250001612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383008530038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071013162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830228300372826532874510100200100002003000030037300371110201100991001001000010000271012163229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010003071012162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071212162229634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000990612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006404163429630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000270612954825100101010000101000050427731303001830037300372828732878510010201000020300003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037224000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000150612954825100101010000101000050427731303001830037300372829932876710010201000020300003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000120612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000016403163329630010000103003830038300383003830038
10024300372250000003672954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000150612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000001562954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006613163329630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  umlal v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722506129548251010010010000100100005004277313130018300373003728265032874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265032874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372240612954825101001001000010010000500428253613001830037300372826503287451010020010000200300003003730037111020110099100100100001000301387101161129634100001003003830038300383003830038
10204300802250612954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000001177101161129634100001003003830038300383003830038
10204300372259612954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000001357101161129634100001003003830038300383003830038
10204300372256612954825101001001000010010000500427731313001830037300372826503287451010020010000200300003003730037111020110099100100100001000001267101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000787101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000697101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265032874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225061295482510100113100001001000050042773131300183003730037282650328745102542001000020030000300373003721102011009910010010000100000277101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000000064051634296300010000103003830038300383003830038
100243003722500000061295302510010101000010101485042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000064041623296300010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000064041634296300210000103003830038300383003830038
100243003722500000061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000000064041634296300010000103003830038300383003830038
1002430037225000000103295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000064031644296300010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000073244143297383010000103018130181301803018030180
10024302752261143546264397529521831003510100241210447714285455030018301323017828287112876710010201000020300003003730083411002110910101000010040122428466241634296680010000103003830038300383003830038
1002430037225000010566166043294851601007712100721211192714290853130306303683055428322402900110010201147520329673032030554711002110910101000010400119563466141633296300010000103003830038300383003830038
100243003724100000061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373008411100211091010100001000000064041634296300010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000000064031634296300010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  umlal v0.4s, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000006129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000010807101161129634100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000014407101161129634100001003003830038300383003830038
1020430037225000000892954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100007507101161129634100001003003830038300383003830038
1020430037225000000699295306310129104100081221029859342786703005430085300842827082876310424204101682043099330133301322110201100991001001000010010554027572253229667100001003013230132301363008630132
102043008522501112888878929548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000013807101161129634100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000013507101161129634100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000013207101161129634100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000010807101161129634100001003003830038300383003830038
10204300372250000906129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000010207101161129634100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427867030018300373003728265328745101002001000020030000300373003711102011009910010010000100001807101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003730106129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100001680640516762963010000103003830038300383003830038
10024300372780612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000150640616672963010000103003830038300383003830038
100243003727806129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100001350640716772963010000103003830038300383003830038
10024300372600612954825100101010000101000055427731303001830037300372828732876710010201017820300003003730037111002110910101000010000180640716772963010000103003830038300383003830038
1002430037260023229548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100001500640716762963010000103003830038300383003830038
1002430037260072629548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100001440640716762963010000103003830038300383003830038
100243003724206129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100001350640716572963010000103003830038300383003830038
100243003724106129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100001440640716762963010000103003830038300383003830038
100243003724106129548251001010100001010000504280027030018300373003728287328767100102010000203000030037300371110021109101010000100001470640616762963010000103003830038300383003830038
100243003724106129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100001470640616662963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  umlal v0.4s, v8.4h, v9.4h
  movi v1.16b, 0
  umlal v1.4s, v8.4h, v9.4h
  movi v2.16b, 0
  umlal v2.4s, v8.4h, v9.4h
  movi v3.16b, 0
  umlal v3.4s, v8.4h, v9.4h
  movi v4.16b, 0
  umlal v4.4s, v8.4h, v9.4h
  movi v5.16b, 0
  umlal v5.4s, v8.4h, v9.4h
  movi v6.16b, 0
  umlal v6.4s, v8.4h, v9.4h
  movi v7.16b, 0
  umlal v7.4s, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042010315000000392580100100800001008041650064000020045200642006432280100200800002002400002006420064111602011009910010016000010000010111116212006101600001002006520065200652006520065
1602042006415000000392580100100800001008000050064000020045200642006432280100200800002002400002006420064111602011009910010016000010010010111116112006101600001002006520065200652006520065
1602042006415000000392580100100800001008000050064000020045200642006432280100200800002002400002006420064111602011009910010016000010000010111116222006101600001002006520065200652006520065
1602042006415100000812580100100800001008000050064000020045200642006432280100200800002002400002006420064111602011009910010016000010000010111116112006101600001002006520065200652006520065
1602042006415000000622580100100800001008000050064000020045200642006432280100200800002002400002006420064111602011009910010016000010000010112116112006101600001002006520065200652006520065
16020420064151000001252580100100800001008000050064000020045200642006432280100200800002002400002006420064111602011009910010016000010000010111116122006101600001002006520065200652006520065
1602042006415000000392580100100800001008000050064000020045200642006432280100200800002002400002006420064111602011009910010016000010000010112116112006101600001002006520065200652006520065
1602042006415000000392580100100800001008000050064000020045200642006432280100200800002002400002006420064111602011009910010016000010000010111116112006101600001002006520065200652006520065
16020420064150000006092580100100800001008000050064000020045200642006432280100200800002002400002006420064111602011009910010016000010000010111116112006101600001002006520065200652006520065
1602042006415000000392580100100800001008000050064000020045200642006432280100200800002002400002006420064111602011009910010016000010000010111116112006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242009915000000145278001212800001280000626400001120032020051200513228001220800002024000020051200511116002110910101600001000000001002531192521124200482201160000102005220052200522005220052
16002420051150000600342278001212800001280000626400001120032020051200513228001220800002024000020051200511116002110910101600001000000001002731122521124200482201160000102005220052200522005220052
16002420051150000000741278001212800001280000626400001120032020051200513228001220800002024000020051200511116002110910101600001000000001002731142521124200482201160000102005220052200522005220052
16002420051150000000755278001212800001280000626400001120293020051200513228001220800002024000020051200511116002110910101600001000000001002731142521124200482201160000102005220052200522005220052
16002420051150000000101278001212800001280000626400001120032020051200513228001220800002024000020051200511116002110910101600001000000001002761135821142200482201160000102005220052200522005220052
16002420051151000900724278001212800001280000626400001120032020051200513228001220800002024000020051200511116002110910101600001000000001002731142521144200482411160000102005220052200522005220052
1600242005115000000059278001212800001280000626400001120034020053200533228032520800002024000020062200511116002110910101600001000010001002831122521142200482401160000102005220052200522005220052
1600242005115000000059278001212800001280000626400001120032020051200513228001220800002024000020051200511116002110910101600001000000001002531142521142200482202160000102006320054202142005220052
1600242005115000000065278001212800001280000626400001120032020051200513228001220800002024000020051200511116002110910101600001000000001002531152521253200482201160000102006320052200522005220052
1600242005115000000065278001212800001280000626433440120034020051200513228001220800002024000020051200511116002110910101600001000000001002631124921142200482201160000102005420052200522005220052

Test 6: throughput

Count: 16

Code:

  umlal v0.4s, v16.4h, v17.4h
  umlal v1.4s, v16.4h, v17.4h
  umlal v2.4s, v16.4h, v17.4h
  umlal v3.4s, v16.4h, v17.4h
  umlal v4.4s, v16.4h, v17.4h
  umlal v5.4s, v16.4h, v17.4h
  umlal v6.4s, v16.4h, v17.4h
  umlal v7.4s, v16.4h, v17.4h
  umlal v8.4s, v16.4h, v17.4h
  umlal v9.4s, v16.4h, v17.4h
  umlal v10.4s, v16.4h, v17.4h
  umlal v11.4s, v16.4h, v17.4h
  umlal v12.4s, v16.4h, v17.4h
  umlal v13.4s, v16.4h, v17.4h
  umlal v14.4s, v16.4h, v17.4h
  umlal v15.4s, v16.4h, v17.4h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044003930000000007102516011710016001710016000050012800000040020400404003919973320006160100200160000200480000400394004811160201100991001001600001000000000010110116114003601600001004004140040400404005040049
160204400393000000000111702516010010016000010016000050013200000140020400484003919973320029160100200160000200480000400494003911160201100991001001600001000000000010110116114006801600001004004040050400404007240041
160204400393000000001780502516010010016000110016000050012800000040020400484003919973319997160100200160000200480000400394004811160201100991001001600001000001000010110116114003601600001004004040040400404032440099
160204400393020000390173802516010110016000010016000050053871880040020400494003919973319997160100200160000200480000400394003911160201100991001001600001000000000010110116114004601600001004004940040400504004040040
16020440048299000000017002516011810016000010016000050013200000040029400394004919973320007160100200160000200480000400394003911160201100991001001600001000000000010110116114003701600001004004040040400504004940040
160204400393000000001720102516016110016000010016000050012800000040030400394003919973319997160100200160000200480000400394003911160201100991001001600001000000000010110116114004501600001004007240049400404004140040
16020440039300000000018002516010010016000010016000050012800000040020400394004919980319997160100200160000200480000400394007111160201100991001001600001000000000010110116114003601600001004004940040400414005040072
16020440039300000000061802516010010016000010016000050023990270140030400394004919973319997160100200160000200480000400394004911160201100991001001600001000000000010110116114003601600001004004040040400404004040040
160204400393000000001790802516011710016000010016000050023990270040020400404003919973319997160100200160000200480000400394004911160201100991001001600001000000000010110116114003601600001004004040040400504004040050
16020440039299000000015002516010110016000010016000050012800001140020400404004919973320006160100200160000200480000400394004811160201100991001001600001000000000010110116114003601600001004004940041400404005040050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)l2 tlb miss instruction (0a)1e1f373a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400513000000000130225160010101600001016000050128000001104002040048400481999603200281600102016000020480000400394003911160021109101016000010000100271652133163221930400364113160000104004040049400414004040049
1600244004830010000171147725160027101600171016000050128000001104002040039400481999603200281600102016000020480000400494004911160021109101016000010000100251692116163223025400364113160000104004040041400404004140041
16002440039300100000122425160010101600171016000050128000001104002140039400392000403200201600102016000020480000400404003911160021109101016000010000100251692117163222918400364113160000104004940040400494004040049
160024400492991000010192425160010101600001016000050128000001104002040039400391999603200191600102016000020480000400394003911160021109101016000010000100271692119163222925400364113160000104004040040400404004040040
1600244003930010000170177125160010101600181016000050128000001104002040049400481999603200281600102016000020480000400394004811160021109101016000010000100251692129163223030400364118160000104004940040400494004040049
160024400483001000001106425160010101600171016000050128000001104002040039400391999603200191600102016000020480000400394003911160021109101016000010222630100271692131583222531400364118160000104004940164400494004040049
1600244004829910133352171824251600111016000010160000501319997011040020400394004819996032001916001020160000204800004003940039111600211091010160000100001002516102127163221829400464113160000104004040040400404004040040
1600244003930010000015225160010101600001016000050128000001104002940138400391999603200191600102016000020480000400494003911160021109101016000010090100271692128163222329400364113160000104004940049400404004040040
160024400493001000001168225160010101600001016000050239899901104002040039400481999603200191600102016000020480000400394004811160021109101016000010000100251692118163222817400364118160000104004940049400494004940049
160024400482991000001169125160027101600171016000050128000001104002040039400401999603200291600102016000020480000400404004021160021109101016000010000100251692130163222931400364118160000104004040040400404004040093