Firestorm: UMLSL2 (vector, 4S) measurements

Code:

  umlsl2 v0.4s, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	10	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	8	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	8	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	82	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3085	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	1	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  umlsl2 v0.4s, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	1	0	1	0	18	1	254	29548	25	10100	100	10000	100	10000	500	4277313	1	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	713	1	0	3	16	5	5	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	1	0	0	1	729	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	4	9	0	713	1	0	6	16	5	5	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	1	1	0	1	64	29548	25	10100	100	10000	100	10000	500	4278079	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	0	713	1	0	5	16	3	5	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	1	0	0	1	349	29548	45	10100	104	10000	102	10000	500	4277313	0	0	30018	30037	30085	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	712	1	0	4	16	5	4	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	1	0	0	1	64	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	713	1	0	3	16	4	4	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	1	0	0	1	64	29548	25	10100	100	10000	100	10000	500	4277313	1	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	713	1	0	5	16	5	5	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	1	0	1	0	0	1	64	29548	25	10100	100	10000	100	10000	500	4277313	1	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	3	0	0	3	0	716	1	0	3	16	5	5	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	1	0	0	1	64	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	0	713	1	0	3	16	3	5	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	1	0	0	2	64	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	713	1	0	3	16	4	5	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	1	0	1	0	357	1	760	29548	25	10100	100	10000	100	10000	500	4277313	0	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	0	712	1	0	6	16	5	5	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5e	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	9	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	3	9	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	1	3	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30085	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	4	5550	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	34	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	38	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	35	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  umlsl2 v0.4s, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	874	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	819	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	10000	100	30086	30038	30038	30038	30038
10204	30037	225	12	212	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	124	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	8	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	103	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	103	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	147	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	145	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	172	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	152	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10176	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	6	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	159	61	29548	25	10010	12	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	60	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	2	0	3	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10012	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10148	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  umlsl2 v0.4s, v1.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	254	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	741	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	170	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	212	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	191	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	9	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	168	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	170	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	84	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	254	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	233	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	84	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	333	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	6	6	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	5	5	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	5	16	5	6	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	6	6	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	5	16	5	4	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	84	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	6	6	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	6	5	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	191	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	5	16	5	5	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	170	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	6	5	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	5	6	29630	0	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  umlsl2 v0.4s, v8.8h, v9.8h
  movi v1.16b, 0
  umlsl2 v1.4s, v8.8h, v9.8h
  movi v2.16b, 0
  umlsl2 v2.4s, v8.8h, v9.8h
  movi v3.16b, 0
  umlsl2 v3.4s, v8.8h, v9.8h
  movi v4.16b, 0
  umlsl2 v4.4s, v8.8h, v9.8h
  movi v5.16b, 0
  umlsl2 v5.4s, v8.8h, v9.8h
  movi v6.16b, 0
  umlsl2 v6.4s, v8.8h, v9.8h
  movi v7.16b, 0
  umlsl2 v7.4s, v8.8h, v9.8h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10112	0	0	0	2	16	0	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	0	0	0	39	65	80100	100	80000	100	80000	500	640000	0	0	20045	20064	20064	3	22	80124	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10112	0	0	0	2	16	0	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10112	0	0	0	5	16	0	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10112	3	0	0	2	16	0	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20134	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10112	0	0	0	2	16	0	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	124	80000	100	80000	500	640000	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10112	0	0	0	2	16	0	2	2	20061	21	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10112	0	0	0	2	16	0	3	3	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20149	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10112	0	0	0	4	25	0	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10114	0	0	0	2	16	0	2	2	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10118	0	0	1	2	16	0	2	2	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20073	150	0	0	0	45	27	80012	12	80000	12	80000	62	640000	1	1	0	20032	0	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	10048	3	1	1	14	25	2	1	1	27	14	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	27	80012	12	80000	12	80000	62	640000	1	0	0	20032	0	20051	20051	3	22	80012	20	80209	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	10048	3	1	1	25	25	2	1	1	13	25	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	27	80012	12	80000	12	80000	62	640000	1	1	5	20032	0	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	10050	8	4	1	25	25	2	1	1	25	31	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	27	80012	12	80000	12	80000	62	640000	1	0	5	20032	0	20060	20051	3	22	80012	20	80000	20	240000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	10039	11	4	2	25	34	4	2	2	13	24	20057	2	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	0	51	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	0	20060	20060	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	10051	11	3	2	25	34	4	2	2	25	25	20057	2	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	0	45	27	80012	12	80000	12	80000	62	640000	1	0	5	20032	0	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	10048	3	2	1	25	25	2	1	1	25	25	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	51	29	80012	12	80000	12	80000	62	640000	0	1	5	20041	0	20060	20060	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	10051	11	3	2	25	34	4	2	2	11	25	20057	2	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	150	0	0	0	50	27	80012	12	80000	12	80000	62	640000	1	1	0	20032	3	20132	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	10048	3	1	1	25	25	2	1	1	13	25	20048	2	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	45	27	80012	12	80000	12	80000	62	640000	1	0	5	20032	0	20051	20051	3	22	80012	20	80000	20	240000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	10034	11	3	1	25	34	2	2	1	11	25	20057	2	40	2	160000	10	20052	20061	20052	20061	20052
160024	20051	150	0	0	0	66	27	80012	12	80000	12	80000	62	640000	1	1	0	20032	0	20051	20051	3	22	80012	20	80000	20	240000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	10034	8	1	1	11	25	2	1	1	13	25	20048	2	20	1	160000	10	20052	20052	20052	20052	20052

Test 6: throughput

Count: 16

Code:

  umlsl2 v0.4s, v16.8h, v17.8h
  umlsl2 v1.4s, v16.8h, v17.8h
  umlsl2 v2.4s, v16.8h, v17.8h
  umlsl2 v3.4s, v16.8h, v17.8h
  umlsl2 v4.4s, v16.8h, v17.8h
  umlsl2 v5.4s, v16.8h, v17.8h
  umlsl2 v6.4s, v16.8h, v17.8h
  umlsl2 v7.4s, v16.8h, v17.8h
  umlsl2 v8.4s, v16.8h, v17.8h
  umlsl2 v9.4s, v16.8h, v17.8h
  umlsl2 v10.4s, v16.8h, v17.8h
  umlsl2 v11.4s, v16.8h, v17.8h
  umlsl2 v12.4s, v16.8h, v17.8h
  umlsl2 v13.4s, v16.8h, v17.8h
  umlsl2 v14.4s, v16.8h, v17.8h
  umlsl2 v15.4s, v16.8h, v17.8h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40051	300	0	0	0	0	0	0	84	0	1	0	707	0	25	160117	100	160017	100	160000	500	2398999	1	5	40021	40039	40040	19973	3	19997	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	0	1	1	16	1	1	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	0	0	0	0	0	6	0	0	0	6645	0	25	160100	100	160000	100	160000	500	1320000	0	0	40021	40040	40039	19973	3	20006	160100	200	160000	200	480000	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	6	0	10110	0	0	1	16	1	1	40036	0	160000	100	40040	40041	40040	40041	40040
160204	40048	300	0	0	0	0	0	0	36	0	0	0	50	0	25	160101	100	160000	100	160000	500	1280000	0	0	40021	40040	40040	19973	3	20029	160100	200	160000	200	480000	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	0	0	1	16	1	1	40037	0	160000	100	40050	40049	40049	40040	40040
160204	40039	300	0	0	0	0	0	0	39	0	1	0	41	0	25	160117	100	160001	100	160000	500	1280000	0	0	40021	40049	40040	19973	3	20007	160100	200	160000	200	480000	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	0	0	1	16	1	1	40036	0	160000	100	40040	40041	40040	40050	40041
160204	40048	300	0	0	0	0	0	0	21	0	1	0	41	0	25	160100	100	160017	100	160000	500	2399027	0	0	40020	40040	40040	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	0	0	1	16	1	1	40037	0	160000	100	40041	40040	40050	40040	40050
160204	40048	300	0	0	0	0	0	0	36	0	0	0	51	0	25	160117	100	160000	100	160000	500	1320000	0	0	40020	40039	40049	19973	3	20007	160100	200	160000	200	480000	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	0	0	1	16	1	1	40037	0	160000	100	40041	40040	40041	40040	40041
160204	40039	299	0	0	0	0	0	0	18	0	1	0	50	0	25	160100	100	160017	100	160000	500	5387188	0	0	40021	40039	40039	19973	3	19997	160100	200	160000	200	480000	40040	40049	1	1	160201	100	99	100	100	160000	100	0	2	0	0	0	0	10110	0	0	1	16	1	1	40046	0	160000	100	40049	40041	40041	40040	40595
160204	40607	304	0	0	1	1	9	10	1506	616	145	1	1915	50	233	161185	125	160626	124	161204	623	1610911	1	5	40608	40309	40604	20167	33	20321	161364	202	160445	200	483957	40645	40552	11	1	160201	100	99	100	100	160000	100	4	0	1	0	3148	4	10293	0	0	1	114	3	8	40621	0	160000	100	40050	40040	40049	40040	40041
160204	40040	300	0	0	0	0	0	0	1689	1056	187	0	1353	126	251	161471	122	161296	121	161351	661	1563334	0	0	40636	40724	40797	20182	56	20399	161207	204	161260	204	485229	40786	40756	13	1	160201	100	99	100	100	160000	100	0	0	2	0	6535	0	10334	0	0	3	151	4	5	40735	24	160000	100	41054	41006	40877	40621	40733
160204	41020	319	2	1	1	1	11	8	939	616	18	0	42	0	25	160101	100	160017	100	160000	500	1280000	0	0	40030	40040	40040	20000	66	20469	162369	200	161937	204	485235	40919	40944	14	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	50	0	1	16	1	6	40045	0	160000	100	40091	40040	40040	40050	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	300	756	0	0	55	25	160010	10	160017	10	160000	50	1280000	1	1	40020	40039	40040	19996	0	3	20029	160010	20	160000	20	480000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	6	16	2	1	1	7	6	40036	15	5	160000	10	40040	40041	40040	40049	40040
160024	40039	300	489	0	0	46	25	160011	10	160017	10	160000	50	1320000	1	1	40020	40039	40040	19996	0	3	20028	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	5	16	2	1	1	5	6	40036	15	5	160000	10	40090	40040	40040	40040	40040
160024	40048	299	525	17	0	46	25	160010	10	160000	10	160000	50	2398999	1	1	40020	40039	40048	19996	0	3	20019	160010	20	160000	20	480000	40039	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	6	16	2	1	1	6	5	40036	15	5	160000	10	40040	40049	40049	40050	40040
160024	40039	299	39	1	0	55	25	160027	10	160000	10	160000	50	2398999	1	1	40020	40039	40048	19996	0	3	20137	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	5	16	2	1	1	7	6	40045	15	5	160000	10	40040	40040	40049	40040	40049
160024	40039	299	90	0	0	46	25	160010	10	160000	10	160000	50	2398999	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	9	16	2	1	1	5	8	40045	15	5	160000	10	40049	40040	40050	40040	40040
160024	40049	300	627	0	0	55	25	160010	10	160000	10	160000	50	2398999	1	1	40020	40039	40048	19996	0	3	20028	160010	20	160000	20	480000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	7	16	2	1	1	7	6	40036	15	5	160000	10	40040	40049	40049	40050	40040
160024	40039	300	486	17	0	55	25	160010	10	160017	10	160000	50	1280000	1	1	40020	40039	40048	19996	0	3	20028	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	3	0	0	0	10022	3	1	1	5	16	2	1	1	6	8	40036	15	5	160000	10	40040	40040	40040	40049	40040
160024	40039	300	687	0	0	46	25	160027	10	160017	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20048	160010	20	160000	20	480000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	2	1	7	16	2	1	1	5	5	40036	15	5	160000	10	40049	40040	40049	40040	40040
160024	40048	300	660	17	0	55	25	160010	10	160001	10	160000	50	1280000	1	1	40020	40048	40039	19996	0	3	20192	160010	20	160000	20	480000	40048	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	2	1	6	16	2	1	1	7	7	40036	15	5	160000	10	40040	40040	40040	40041	40040
160024	40040	300	669	0	0	47	25	160027	10	160000	10	160000	50	2399027	1	1	40020	40039	40040	19996	0	3	20028	160010	20	160000	20	480000	40049	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	7	16	2	1	1	7	7	40036	15	5	160000	10	40041	40040	40040	40040	40040

UMLSL2 (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations