Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMLSL (by element, 4S)

Test 1: uops

Code:

  umlsl v0.4s, v1.4h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000300030373037111001100007873116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000300030373037111001100006373116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000300030373037111001100006673116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000300030373037111001100006373116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000300030373037111001100007573116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  umlsl v0.4s, v1.4h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240000013102954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000071014163329634100001003003830038300383003830038
10204300372250000010242954825101001001000010010000500427731313001803003730037282653287451010020010000200300003003730037111020110099100100100001000071013163429634100001003003830038300383003830038
10204300372250000016332954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000071013163329634100001003003830038300383003830038
102043003722500000612954825101001001000010010000522427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000071013163329634100001003003830038300383003830038
10204300372250000010172954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000071013163329634100001003003830038300383003830038
10204300372240000011432954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000071013164329634100001003003830038300383003830038
10204300372250000010052954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000071014163429634100001003003830038300383003830038
10204300372240000011552954825101001001000010010000500427731303001803003730037282653287451010020010000204300003003730037111020110099100100100001000071013163329634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000071013163429634100001003003830038300383003830038
1020430037225000001662954825101001001000010010000500427731303001803003730037282653287451010020010000200300003003730037111020110099100100100001000071013163329634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100180640316332963010000103003830038300383003830038
100243003722500061295482510010101000810100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640316332963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010001640316332963010000103003830038300383003830038
1002430037225000548295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216332963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216322963010000103003830038300383003830038
1002430037224000979295302510010101000010100005042773133001830037300372828732876710010201000020300003017930037111002110910101000010000640316332963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640316332963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
100253003722400061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640316332963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773133001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103008530038300383003830038

Test 3: Latency 1->2

Code:

  umlsl v0.4s, v0.4h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722400000001227295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071021611296340100001003003830038300383003830038
102043003722400000001068295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
102043003722500000001168295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830085
102043003722500000001031295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000934295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000890295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
102043003722400000001047295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000975295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000100071011611296340100001003003830038300383003830038
102043003722500000001002295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000994295482510100104100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011612296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250005972954825100101010000101000050427731313001803003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372250007972954825100101010000101000050427731313001803003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372250009322954825100101010000101000050427731313001803003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372250004192954825100101010000101000050427731303001803003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372250004282954825100101010000101000050427731303001803003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500011232954825100101010000101000050427731303001803003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372250006492954825100101010000101000050427731303001803003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830086
10024300372250001872954825100101010000101000050427731303001803003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500011122954825100101010000101000050427731303001803003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500011132954825100101010000101000050427731303001803003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  umlsl v0.4s, v1.4h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722502761295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250661295482510100100100001001000050042773131300180300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037224000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006424164429632010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710159201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
100243003722400016022952125100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710012201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006424164429632210000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006402162229630010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  umlsl v0.4s, v8.4h, v9.h[1]
  movi v1.16b, 0
  umlsl v1.4s, v8.4h, v9.h[1]
  movi v2.16b, 0
  umlsl v2.4s, v8.4h, v9.h[1]
  movi v3.16b, 0
  umlsl v3.4s, v8.4h, v9.h[1]
  movi v4.16b, 0
  umlsl v4.4s, v8.4h, v9.h[1]
  movi v5.16b, 0
  umlsl v5.4s, v8.4h, v9.h[1]
  movi v6.16b, 0
  umlsl v6.4s, v8.4h, v9.h[1]
  movi v7.16b, 0
  umlsl v7.4s, v8.4h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)dadbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008915000392580100100800001008000050064000001200452006420064322801002008000020024000020064200641116020110099100100160000100000101110001160011200611600001002006520065200652006520065
16020420064150330392580100100800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100000101110001160011200611600001002007820078200782006520065
1602042007715000392780100100800001008000050064000000200452006420064322801002008000020024000020064200641116020110099100100160000100000101110001160011200611600001002006520065200652006520065
1602042006415000392580100100800001008000050064000000200452006420064322801242008000020024000020077200771116020110099100100160000100003101110001160011200611600001002006520065200652006520065
1602042006415000392580100100800001008000050064000001200452006420064322801002008000020024000020064200641116020110099100100160000100000101110001160011200611600001002006520065200652006520065
16020420064150150392580100100800001008000050064000011200452006420064322801002008000020024000020064200641116020110099100100160000100000101110003160032200611600001002006520065200652006520065
16020420064151240392580100100800001008000050064000001200452006420064322801002008000020024000020064200641116020110099100100160000100000101110001160011200611600001002006520065200782006520065
16020420064150270392580100100800001008000050064000001200452006420064322801002008000020024000020064200641116020110099100100160000100000101110001160011200611600001002006520065200652006520065
16020420064150240392580100100800001008000050064000001200452006420064322801002008000020024000020064200641116020110099100100160000100000101110001160011200611600001002006520065200652006520065
160204200641507200392580100100800001008000050064000001200452006420064322801002008000020024000020064200641116020110099100100160000100000101110001160011200611600001002007820078200652007820065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)c9cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200811500001504525800121280000128000062640000115200272004620046322800122080000202400002004620046111600211091010160000100000000001002781255202114420043215160000102004720047200472004720047
160024200461500000045258001212800001280000626400001152002720046200463228001220800002024000020050200501116002110910101600001000000000010032114234244226620047230160000102005120051200512005120051
160024200501500000051258001212800001280000626400000152003120050200503228001220800002024000020050200501116002110910101600001000000000010031114194244225520047230160000102005120051200512005120051
160024200501500000051258001212800001280000626400000152003120050200503228001220800002024000020050200501116002110910101600001000000000010031114184244225420043230160000102005120051200512005120051
16002420050150000004525800121280000128000062640000015200272005020050322800122080000202400002005020046111600211091010160000100000000001003185165244215520047215160000102005120047200512005120051
160024200461500000051258001212800001280000626400000152002720050200503228001220800002024000020050200461116002110910101600001000000000010031115196244126620043230160000102004720051200512004720051
160024200501500000045258001212800001280000626400000152002720050200503228001220800002024000020046200501116002110910101600001000000000010031115164244125620043230160000102004720051200512004720051
160024200501510000071725800121280000128000062640000115200312005020046322800122080000202400002004620050111600211091010160000100000000001003285195243225420047230160000102005120051200472005120047
160024200461500000051258001212800001280000626400000152002720050200503228001220800002024000020050200461116002110910101600001000000000010031115185244216520047230160000102005120051200512005120051
16002420046150000005125800121280000128000062640000115200312005020046322800122080000202400002005020046111600211091010160000100000000001003185185202224520047215160000102005120047200512005120051

Test 6: throughput

Count: 12

Code:

  umlsl v0.4s, v12.4h, v13.h[1]
  umlsl v1.4s, v12.4h, v13.h[1]
  umlsl v2.4s, v12.4h, v13.h[1]
  umlsl v3.4s, v12.4h, v13.h[1]
  umlsl v4.4s, v12.4h, v13.h[1]
  umlsl v5.4s, v12.4h, v13.h[1]
  umlsl v6.4s, v12.4h, v13.h[1]
  umlsl v7.4s, v12.4h, v13.h[1]
  umlsl v8.4s, v12.4h, v13.h[1]
  umlsl v9.4s, v12.4h, v13.h[1]
  umlsl v10.4s, v12.4h, v13.h[1]
  umlsl v11.4s, v12.4h, v13.h[1]
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
12020430059227000000690070602512010010012000010012000050042834001300233003930039149733149971201002001200002003600003003930039111202011009910010012000010000000007610116113003901200001003004030043300403004030040
12020430039232000000159017060251201011001200001001200005009900000300203003930039149733159011201002001200002003600003094330039111202011009910010012000010000000007610116113003601200001003004030040300433004030944
1202043044322500000032400413489251201001001200011001200005009600000309243174330039149733149971201002001200002003600003003930042111202011009910010012000010000000007610116113003601200001003094430040300403094430040
12020430039231000000345004240251201171001200011001200005009900000309243003930942149733149971201002001200002003600003003930922111202011009910010012000010000000007610151113003901200001003004130040300403004330040
12020430042225000000291017060251201011001200001001200006119600000300203100230039149733149971201002001200002003600003003930943111202011009910010012000010000000007610116113003601200001003004030040309443004030043
12020430039225000000369017060251201001001200001001200005009600000300203003930040149733149971201002001200002003600003003930042111202011009910010012000010000040607610116113003601200001003004030040300433004030944
1202043003922500000030018360251201001001200001001200005009600000300233003930042149733150001201002001200002003600003003930042111202011009910010012000010000000007610116113003601200001003004030923300403004030040
12020430039225000000324009220251201011001200001001200005009600000300203256430039149733159011201002001200002003600003004230039111202011009910010012000010000000007610116113003901200001003004030043300403004030923
120204300392250000003900613489251201001001200011001200005009600000300203003930039149733159011201002001200002003600003094330039111202011009910010012000010000000007610116113003601200001003004030040312783004030040
120204300392250000002400613489251201001001200531001200005009600000317143003930039155803149971201002001200002003604323092230039111202011009910010012000010000000007610116113003901200001003004030040300433004030043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)031e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
120024305822324504002512001010120000101200005096000010300200317613003916677031501912001020120000203600003003930039111200211091010120000100000752000016167103003600120000103004030040300403004030040
12002430039225240400251200101012000010120000509600001530020031761300391499603150191200102012000020360000300393003911120021109101012000010000075200006166123003600120000103004030040309523004030040
12002430039225604002512001010120000101200005096000000300200300393004014996031502012001020120000203600003003930039111200211091010120000100000752000041612113003600120000103004030040300403004030040
1200243003922524061671825120010101200001012000050960000003002003004230039149960315019120010201200002036000030039300391112002110910101200001000007520000516563003600120000103004030040300403004030040
120024300392250040025120010101200001012000050960000053002003003930039149960315019120010201200002036000030922300421112002110910101200001000007520010416493003600120000103004030040300403004030040
1200243003922560610251200101012000010120000509600000030020030039300391499603150191200102012000020360000300393003911120021109101012000010000075200004161173003605120000103004030040300403004030040
12002430039225330400251200101012000010120000509600000030020030040300391499603150191200102012000020360000300393003911120021109101012000010000075200005161163003600120000103004030040300403004030040
120024300392252310400251200111012000010120000509600001030020030039300391499603150191200102012000020360000300393003911120021109101012000010000075200107165123003600120000103004030040300403004030040
120024300392250040025120010101200001012000050960000103002003176130039149960315019120010201200002036000030039300391112002110910101200001000007520500516653003600120000103004030040300403004030040
120024300392240040025120010101200001012000050960000053002003176130040166760315019120010201200002036000030039300391112002110910101200001000007520000516573003600120000103004030040300403004030040