Firestorm: UMLSL (vector, 8H) measurements

Code:

  umlsl v0.8h, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	82	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	293	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	2	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	2	1	1	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	429	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	253	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  umlsl v0.8h, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	82	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	2742	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	3	29670	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	4317	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	1	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	631	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	441	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	726	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	726	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	4	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	536	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	4	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	251	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	726	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	726	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	17	0	24	0	640	3	16	3	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	145	29548	25	10010	10	10000	10	10000	50	4277313	1	30126	30132	30037	28287	3	28767	10010	20	10000	20	30000	30082	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	4	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  umlsl v0.8h, v0.8b, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	24	79	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	710	0	1	26	1	1	29634	10	10000	100	30038	30038	30038	30038	30038
10204	30037	225	18	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	27	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	27	61	29548	25	10100	100	10000	100	10000	500	4278672	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	2	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	27	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	36	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10268	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	27	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	21	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	24	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	27	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	726	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	251	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30133	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	1	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	3	29630	0	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  umlsl v0.8h, v1.8b, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	42	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30179	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	2849	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	4	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	9	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4278093	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30228	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	9	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	246	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28303	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	15	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	20	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	21	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	282	0	726	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	1	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	441	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	747	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  umlsl v0.8h, v8.8b, v9.8b
  movi v1.16b, 0
  umlsl v1.8h, v8.8b, v9.8b
  movi v2.16b, 0
  umlsl v2.8h, v8.8b, v9.8b
  movi v3.16b, 0
  umlsl v3.8h, v8.8b, v9.8b
  movi v4.16b, 0
  umlsl v4.8h, v8.8b, v9.8b
  movi v5.16b, 0
  umlsl v5.8h, v8.8b, v9.8b
  movi v6.16b, 0
  umlsl v6.8h, v8.8b, v9.8b
  movi v7.16b, 0
  umlsl v7.8h, v8.8b, v9.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	150	0	39	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	0	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10114	5	1	0	2	16	0	0	0	4	4	20061	0	0	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	0	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10114	5	0	0	3	16	0	0	0	5	5	20061	0	0	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	39	25	80100	100	80000	100	80000	500	640000	1	1	5	20045	0	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10113	5	0	0	4	16	0	0	0	4	4	20061	0	0	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	0	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10115	5	1	0	4	16	0	0	0	5	3	20061	0	0	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	0	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10114	5	1	0	5	16	0	0	0	5	4	20061	0	0	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	0	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10113	5	1	0	4	16	0	0	0	5	4	20061	0	0	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	0	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10114	5	1	0	4	16	2	2	0	4	4	20061	0	0	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	0	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10115	5	1	0	5	16	0	0	0	5	4	20061	0	0	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	60	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	0	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10115	5	0	0	5	16	0	0	0	5	4	20061	0	0	0	160000	100	20065	20065	20065	20065	20065
160204	20074	150	6	39	25	80100	100	80000	100	80000	500	640000	0	1	5	20045	0	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	10115	0	0	0	5	16	0	0	0	5	4	20061	0	0	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20073	150	0	45	25	80012	12	80000	12	80000	62	640000	2	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10025	3	1	1	5	20	2	1	1	2	4	20043	2	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	51	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10028	6	2	2	8	24	4	2	2	4	4	20047	2	30	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	45	25	80012	12	80000	12	80000	62	640000	2	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10027	3	1	1	4	20	2	1	1	4	2	20043	2	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10027	3	1	1	4	20	2	1	1	4	2	20043	2	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	3	10027	3	1	1	4	20	2	1	1	4	2	20043	2	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10027	3	1	1	2	20	2	1	1	4	2	20043	2	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	201	45	25	80012	12	80000	12	80000	62	640000	0	1	20031	20050	20050	3	22	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	10027	3	1	1	4	20	2	1	1	2	4	20043	2	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	213	51	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10025	3	1	1	2	20	2	1	1	4	2	20043	2	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	31	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10027	3	1	1	4	20	2	1	1	2	4	20043	2	15	160000	10	20047	20047	20047	20047	20047
160024	20046	151	0	45	25	80012	12	80000	12	80000	62	640000	1	1	20027	20046	20046	3	22	80012	20	80000	20	240000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10027	3	1	1	2	20	2	1	1	4	4	20043	2	15	160000	10	20047	20047	20047	20047	20047

Test 6: throughput

Count: 16

Code:

  umlsl v0.8h, v16.8b, v17.8b
  umlsl v1.8h, v16.8b, v17.8b
  umlsl v2.8h, v16.8b, v17.8b
  umlsl v3.8h, v16.8b, v17.8b
  umlsl v4.8h, v16.8b, v17.8b
  umlsl v5.8h, v16.8b, v17.8b
  umlsl v6.8h, v16.8b, v17.8b
  umlsl v7.8h, v16.8b, v17.8b
  umlsl v8.8h, v16.8b, v17.8b
  umlsl v9.8h, v16.8b, v17.8b
  umlsl v10.8h, v16.8b, v17.8b
  umlsl v11.8h, v16.8b, v17.8b
  umlsl v12.8h, v16.8b, v17.8b
  umlsl v13.8h, v16.8b, v17.8b
  umlsl v14.8h, v16.8b, v17.8b
  umlsl v15.8h, v16.8b, v17.8b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	300	0	0	0	1	41	25	25	160100	100	160000	100	160000	500	2399027	0	40020	40040	40049	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40049	40049	40049	40040	40049
160204	40048	300	0	0	0	17	51	0	25	160100	100	160000	100	160000	500	1320000	1	40020	40039	40049	19973	3	19997	160100	200	160000	200	480000	40172	40132	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40041	40040	40041	40040	40041
160204	40040	299	0	0	0	1	42	0	25	160100	100	160000	100	160000	500	1320000	1	40021	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40049	40040	40040	40040	40040
160204	40048	299	0	0	0	0	41	0	25	160100	100	160000	100	160000	500	1280000	1	40020	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40046	160000	100	40049	40049	40049	40049	40040
160204	40039	300	0	0	0	0	71	0	25	160100	100	160000	100	160000	500	1320000	0	40020	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40049	40040	40040	40040	40040
160204	40039	300	0	0	0	0	41	0	25	160100	100	160000	100	160000	500	1280000	1	40029	40039	40039	19973	3	19997	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40045	160000	100	40049	40040	40049	40040	40049
160204	40048	300	0	0	0	0	41	0	25	160100	100	160000	100	160000	500	1280000	0	40020	40039	40048	19973	3	20006	160100	200	160000	200	480000	40099	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40040	40049	40040	40049	40049
160204	40049	300	0	0	0	0	50	0	25	160100	100	160000	100	160000	500	2438865	1	40020	40039	40039	19973	3	19997	160100	200	160000	200	480000	40048	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40045	160000	100	40049	40040	40049	40040	40040
160204	40039	300	0	0	0	0	41	0	25	160100	100	160000	100	160000	500	1280000	0	40020	40039	40048	19973	3	20006	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40040	40040	40040	40041	40049
160204	40039	299	0	15	0	17	50	0	25	160117	100	160017	100	160000	500	1280000	1	40029	40039	40048	19973	3	19997	160100	200	160000	200	480000	40039	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40040	40049	40040	40049	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40048	300	1	0	0	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	2368574	1	1	40020	40039	40039	19996	3	20028	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	20	16	2	1	1	20	13	40036	15	5	0	160000	10	40050	40050	40041	40049	40040
160024	40040	300	0	0	0	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	2725319	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	16	16	2	1	1	18	17	40036	15	5	0	160000	10	40040	40040	40040	40040	40040
160024	40048	300	0	0	0	0	0	0	0	0	55	0	25	160010	10	160000	10	160000	50	2558962	2	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	18	16	2	1	1	17	20	40045	15	5	0	160000	10	40040	40040	40040	40040	40050
160024	40039	300	0	0	0	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1356137	0	1	40020	40039	40040	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	6	1	2	18	16	4	2	2	18	17	40036	30	10	0	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	570	0	0	52	0	25	160010	10	160001	10	160000	50	1319997	0	1	40029	40039	40039	19996	3	20019	160010	20	160000	20	480396	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	6	1	2	17	16	2	2	1	18	17	40036	15	10	0	160000	10	40049	40040	40040	40040	40040
160024	40039	299	0	0	0	0	0	0	0	0	236	0	25	160010	11	160109	10	160000	50	1319997	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	16	16	2	1	1	18	16	40036	15	5	0	160000	10	40127	40040	40040	40040	40040
160024	40052	300	0	0	0	0	0	0	0	1	46	0	25	160027	10	160000	10	160000	50	2398999	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	13	16	2	1	1	15	16	40036	15	5	0	160000	10	40040	40040	40040	40041	40041
160024	40052	300	0	0	0	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40048	40048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	19	16	2	1	1	21	18	40036	15	5	0	160000	10	40040	40040	40040	40040	40040
160024	40040	300	0	0	0	1	2	420	192	38	658	4	64	160271	12	160337	12	160314	61	1314405	1	1	40161	40164	40242	20043	11	20112	160222	20	160209	20	480606	40191	40205	4	1	160021	10	9	10	10	160000	10	2	2	2	2	0	2	1295	0	10022	3	1	1	18	16	2	1	1	17	18	40036	15	5	0	160000	10	40049	40040	40040	40040	40040
160024	40040	300	0	0	0	0	0	0	0	0	46	0	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	16	16	2	1	1	16	16	40036	15	5	0	160000	10	40040	40040	40040	40040	40040

UMLSL (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations