Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMLSL (vector, 8H)

Test 1: uops

Code:

  umlsl v0.8h, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220822548251000100010003983131301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
100430372202932548251000100010003983131301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
10043037220822548251000100010003983130301830373037241532895100010003000303730371110011000002073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010003000303730371110011000211073116112630100030383038303830383038
100430372304292548251000100010003983131301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
10043037220612548251000100010003983131301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
100430372302532548251000100010003983131301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
10043037220612548251000100010003983131301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038
10043037220612548251000100010003983131301830373037241532895100010003000303730371110011000000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  umlsl v0.8h, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03183a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225008229548251010010010000100100005004277313030018300373003728265328745101002001000020030000300373003711102011009910010010000100007101216222963400100001003003830038300383003830038
102043003722500274229548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101216222963400100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101216222963400100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101216232967000100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101216222963400100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101216222963400100001003003830038300383003830038
102043003722500431729548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101216222963400100001003003830038300383003830038
1020430037225016129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101216222963400100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101216222963400100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101216222963400100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000631295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006404163329630010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
100243003722500000441295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
100243003722400000726295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
100243003722500000726295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006403164329630010000103003830038300383003830038
100243003722500000536295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006404164329630010000103003830038300383003830038
100243003722500000251295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
100243003722500000726295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000000006403163329630010000103003830038300383003830038
10024300372250000072629548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100001702406403163329630010000103003830038300383003830038
100243003722500000145295482510010101000010100005042773131301263013230037282873287671001020100002030000300823003711100211091010100001000000006403163429630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  umlsl v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225247929548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100107100126112963410100001003003830038300383003830038
102043003722518612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
102043003722527612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
102043003722527612954825101001001000010010000500427867203001830037300372826532874510100200100002003000030037300371110201100991001001000010000710011621296340100001003003830038300383003830038
102043003722527612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
102043003722536612954825101001001000010010000500427731303001830037300372826532874510268200100002003000030037300371110201100991001001000010000710021611296340100001003003830038300383003830038
102043003722527612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
102043003722521612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
102043003722524612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
102043003722527612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295482510010101000010100005042773130300180300373003728287328767100102010000203000030037300371110021109101010000100006403162229630010000103003830038300383003830038
10024300372250726295482510010101000010100005042773130300180300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250251295482510010101000010100005042773130300180300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300180300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037224061295482510010101000010100005042773131300180300373003728287328767100102010000203000030133300371110021109101010000100006402162229630110000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300180300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300180300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300180300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300180300373003728287328767100102010000203000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300180300373003728287328767100102010000203000030037300371110021109101010000100006402162329630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  umlsl v0.8h, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372254206129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373017928265328745101002001000020030000300373003711102011009910010010000100028497101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100407101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225906129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004278093130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373022828265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225906129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225024606129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018300373003728303328767100102010000203000030037300371110021109101010000102000000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
100243003722501506129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282872028767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
100243003722502106129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
10024300372250282072629548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000001640216222963010000103003830038300383003830038
100243003722500044129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038
100243003722500074729548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000000640216222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  umlsl v0.8h, v8.8b, v9.8b
  movi v1.16b, 0
  umlsl v1.8h, v8.8b, v9.8b
  movi v2.16b, 0
  umlsl v2.8h, v8.8b, v9.8b
  movi v3.16b, 0
  umlsl v3.8h, v8.8b, v9.8b
  movi v4.16b, 0
  umlsl v4.8h, v8.8b, v9.8b
  movi v5.16b, 0
  umlsl v5.8h, v8.8b, v9.8b
  movi v6.16b, 0
  umlsl v6.8h, v8.8b, v9.8b
  movi v7.16b, 0
  umlsl v7.8h, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042009115003925801001008000010080000500640000015200450200642006432280100200800002002400002006420064111602011009910010016000010001011451021600044200610001600001002006520065200652006520065
1602042006415003925801001008000010080000500640000015200450200642006432280100200800002002400002006420064111602011009910010016000010001011450031600055200610001600001002006520065200652006520065
1602042006415103925801001008000010080000500640000115200450200642006432280100200800002002400002006420064111602011009910010016000010001011350041600044200610001600001002006520065200652006520065
1602042006415003925801001008000010080000500640000015200450200642006432280100200800002002400002006420064111602011009910010016000010001011551041600053200610001600001002006520065200652006520065
1602042006415003925801001008000010080000500640000015200450200642006432280100200800002002400002006420064111602011009910010016000010001011451051600054200610001600001002006520065200652006520065
1602042006415003925801001008000010080000500640000015200450200642006432280100200800002002400002006420064111602011009910010016000010001011351041600054200610001600001002006520065200652006520065
1602042006415003925801001008000010080000500640000015200450200642006432280100200800002002400002006420064111602011009910010016000010001011451041622044200610001600001002006520065200652006520065
1602042006415003925801001008000010080000500640000015200450200642006432280100200800002002400002006420064111602011009910010016000010001011551051600054200610001600001002006520065200652006520065
1602042006415106025801001008000010080000500640000015200450200642006432280100200800002002400002006420064111602011009910010016000010001011550051600054200610001600001002006520065200652006520065
1602042007415063925801001008000010080000500640000015200450200642006432280100200800002002400002006420064111602011009910010016000010001011500051600054200610001600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200731500452580012128000012800006264000021200272004620046322800122080000202400002004620046111600211091010160000100100253115202112420043215160000102004720047200472004720047
160024200461500512580012128000012800006264000011200272004620046322800122080000202400002004620046111600211091010160000100100286228244224420047230160000102005120051200512005120051
160024200501500452580012128000012800006264000021200272004620046322800122080000202400002004620046111600211091010160000100100273114202114220043215160000102004720047200472004720047
160024200461500452580012128000012800006264000011200272004620046322800122080000202400002004620046111600211091010160000100100273114202114220043215160000102004720047200472004720047
160024200461500452580012128000012800006264000011200272004620046322800122080000202400002004620046111600211091010160000103100273114202114220043215160000102004720047200472004720047
160024200461500452580012128000012800006264000011200272004620046322800122080000202400002004620046111600211091010160000100100273112202114220043215160000102004720047200472004720047
16002420046150201452580012128000012800006264000001200312005020050322800122080000202400002005020050111600211091010160000100100273114202112420043215160000102004720047200472004720047
16002420046150213512580012128000012800006264000011200272004620046322800122080000202400002004620046111600211091010160000100100253112202114220043215160000102004720047200472004720047
1600242004615004525800121280000128000062640000112002720046200463122800122080000202400002004620046111600211091010160000100100273114202112420043215160000102004720047200472004720047
160024200461510452580012128000012800006264000011200272004620046322800122080000202400002004620046111600211091010160000100100273112202114420043215160000102004720047200472004720047

Test 6: throughput

Count: 16

Code:

  umlsl v0.8h, v16.8b, v17.8b
  umlsl v1.8h, v16.8b, v17.8b
  umlsl v2.8h, v16.8b, v17.8b
  umlsl v3.8h, v16.8b, v17.8b
  umlsl v4.8h, v16.8b, v17.8b
  umlsl v5.8h, v16.8b, v17.8b
  umlsl v6.8h, v16.8b, v17.8b
  umlsl v7.8h, v16.8b, v17.8b
  umlsl v8.8h, v16.8b, v17.8b
  umlsl v9.8h, v16.8b, v17.8b
  umlsl v10.8h, v16.8b, v17.8b
  umlsl v11.8h, v16.8b, v17.8b
  umlsl v12.8h, v16.8b, v17.8b
  umlsl v13.8h, v16.8b, v17.8b
  umlsl v14.8h, v16.8b, v17.8b
  umlsl v15.8h, v16.8b, v17.8b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400593000001412525160100100160000100160000500239902704002040040400491997331999716010020016000020048000040039400391116020110099100100160000100000001011011611400361600001004004940049400494004040049
160204400483000001751025160100100160000100160000500132000014002040039400491997331999716010020016000020048000040172401321116020110099100100160000100000001011011611400361600001004004140040400414004040041
16020440040299000142025160100100160000100160000500132000014002140039400391997331999716010020016000020048000040039400391116020110099100100160000100000001011011611400361600001004004940040400404004040040
16020440048299000041025160100100160000100160000500128000014002040039400391997331999716010020016000020048000040039400391116020110099100100160000100000001011011611400461600001004004940049400494004940040
16020440039300000071025160100100160000100160000500132000004002040039400391997331999716010020016000020048000040039400401116020110099100100160000100000001011011611400361600001004004940040400404004040040
16020440039300000041025160100100160000100160000500128000014002940039400391997331999716010020016000020048000040048400391116020110099100100160000100000001011011611400451600001004004940040400494004040049
16020440048300000041025160100100160000100160000500128000004002040039400481997332000616010020016000020048000040099400391116020110099100100160000100000001011011611400361600001004004040049400404004940049
16020440049300000050025160100100160000100160000500243886514002040039400391997331999716010020016000020048000040048400391116020110099100100160000100000001011011611400451600001004004940040400494004040040
16020440039300000041025160100100160000100160000500128000004002040039400481997332000616010020016000020048000040039400391116020110099100100160000100000001011011611400361600001004004040040400404004140049
1602044003929901501750025160117100160017100160000500128000014002940039400481997331999716010020016000020048000040039400481116020110099100100160000100000001011011611400361600001004004040049400404004940040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400483001000000046025160010101600001016000050236857411400204003940039199963200281600102016000020480000400394003911160021109101016000010000000001002231120162112013400361550160000104005040050400414004940040
160024400403000000000046025160010101600001016000050272531911400204003940039199963200191600102016000020480000400394003911160021109101016000010000000001002231116162111817400361550160000104004040040400404004040040
160024400483000000000055025160010101600001016000050255896221400204003940039199963200191600102016000020480000400394003911160021109101016000010000000001002231118162111720400451550160000104004040040400404004040050
1600244003930000000000460251600101016000010160000501356137014002040039400401999632001916001020160000204800004003940039111600211091010160000100000000010022612181642218174003630100160000104004040040400404004040040
160024400393000000057000520251600101016000110160000501319997014002940039400391999632001916001020160000204803964003940039111600211091010160000100000000010022612171622118174003615100160000104004940040400404004040040
1600244003929900000000236025160010111601091016000050131999711400204003940039199963200191600102016000020480000400394003911160021109101016000010000000001002231116162111816400361550160000104012740040400404004040040
160024400523000000000146025160027101600001016000050239899911400204003940039199963200191600102016000020480000400394003911160021109101016000010000000001002231113162111516400361550160000104004040040400404004140041
160024400523000000000046025160010101600001016000050128000011400204003940039199963200191600102016000020480000400484004811160021109101016000010000000001002231119162112118400361550160000104004040040400404004040040
1600244004030000012420192386584641602711216033712160314611314405114016140164402422004311201121602222016020920480606401914020541160021109101016000010222202129501002231118162111718400361550160000104004940040400404004040040
160024400403000000000046025160010101600001016000050128000011400204003940039199963200191600102016000020480000400394003911160021109101016000010000000001002231116162111616400361550160000104004040040400404004040040