Firestorm: UMOV (B to W) measurements

Code:

  umov w0, v0.b[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	1	0	85	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	64	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	5	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	0	3	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	3	73	3	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	0	12	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	27	73	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	71	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	4	16	4	4	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  umov w0, v0.b[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100038	775	0	0	0	0	1	12	0	0	100026	89561	25	30100	10100	10000	10000	100	10000	10050	500	4778481	5580517	0	100013	0	100117	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100120	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	1	0	0	0	0	88	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	0	100038	100038	96900	77	98135	20452	200	10000	10000	200	10000	10000	100038	100040	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	1331	1	16	1	1	99637	10000	10000	10100	100039	100039	100040	100041	100039
20204	100038	775	0	0	0	0	0	0	0	0	100106	89561	25	30100	10100	10002	10000	100	10000	10000	500	4778481	5580349	0	100013	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	1310	1	25	1	1	99637	10000	10000	10100	100042	100039	100039	100039	100040
20204	100038	775	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10059	10000	500	4778481	5580349	0	100013	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10060	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3483	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	12	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778625	5580349	0	100013	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	3	0	3	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100125	100039	100039
20204	100038	776	0	0	0	0	0	0	0	0	100024	89603	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	0	100038	100038	96900	3	97496	20100	202	10000	10000	200	10000	10000	100038	100039	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100043	100041	100039	100039
20204	100038	775	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580462	0	100014	0	100038	100038	96902	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100039	775	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10050	500	4778481	5580349	0	100014	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	21	0	0	100026	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778577	5580349	0	100013	0	100039	100041	96903	3	97568	20100	200	10000	10000	200	10000	10000	100049	100039	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100040	775	0	0	0	12	0	100196	89600	45	30032	10013	10002	10006	11	10174	10567	78	4826378	5678785	0	100155	100122	100291	97019	11	97576	20117	20	10181	10060	20	10121	10121	100209	100120	4	1	20021	10	9	10	10010	10000	10	2	0	10004	0	0	10311	0	1306	3	32	3	4	99637	10046	3	0	0	10000	10010	100126	100129	100039	100039	100039
20024	100128	776	0	0	0	141	88	100102	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	3	16	3	3	99637	10000	0	0	0	10000	10010	100039	100039	100039	100042	100039
20024	100039	775	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100039	100150	5	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	3	16	3	3	99637	10000	0	0	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	12	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579178	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100039	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	3	16	3	3	99637	10000	0	4	1	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100102	100038	100087	96922	3	97521	20117	20	10000	10000	20	10000	10000	100038	100038	1	1	20022	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	1270	3	16	3	3	99637	10000	0	0	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100041	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	1270	3	16	3	3	99637	10000	0	0	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97525	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	1270	3	16	3	3	99638	10000	0	0	0	10000	10010	100039	100039	100042	100039	100039
20024	100040	775	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778721	5579234	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100134	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	3	16	3	3	99637	10000	0	0	0	10000	10010	100039	100039	100039	100039	100039
20024	100039	775	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	3	16	3	3	99638	10000	0	0	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778673	5578954	0	100013	100038	100038	96925	3	97518	20010	20	10000	10000	20	10000	10000	100039	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	3	16	3	3	99637	10000	0	0	0	10000	10010	100039	100039	100039	100039	100039

Test 3: throughput

Count: 8

Code:

  umov w0, v8.b[1]
  umov w1, v8.b[1]
  umov w2, v8.b[1]
  umov w3, v8.b[1]
  umov w4, v8.b[1]
  umov w5, v8.b[1]
  umov w6, v8.b[1]
  umov w7, v8.b[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40051	322	0	0	0	0	12	0	32	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	120	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	0	0	0	507	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	159	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	322	0	0	0	0	3	0	74	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	150	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40045	321	0	0	0	0	0	0	75	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	87	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	0	3	0	32	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	102	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	0	6	0	60	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	39	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	102	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	0	6	0	53	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	105	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	322	0	0	0	0	0	0	42	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	123	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	0	0	0	32	25	160100	80100	80000	102	80004	505	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	3	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	322	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	129	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40038	322	0	0	9	0	0	2024	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29985	3	30011	80010	20	80000	20	80089	40038	40038	1	1	80021	10	9	10	80010	10	2	2	0	2838	2	0	5104	11	56	14	16	40198	80232	80010	40104	40303	40430	40369	40427
80024	40369	325	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29985	3	30011	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	3	0	0	0	0	5020	16	16	14	7	40035	80000	80010	40106	40039	40039	40039	40039
80024	40038	321	1	0	0	0	0	548	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29985	3	30011	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	3	0	3	0	0	5020	17	16	16	16	40035	80000	80010	40105	40039	40039	40039	40039
80024	40038	321	0	0	0	598	0	211	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29985	3	30011	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	8	16	14	14	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	0	0	0	708	25	160010	80010	80077	10	80000	50	640646	0	40019	40038	40038	30017	3	30011	80010	20	80000	20	80000	40038	40038	2	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	17	16	13	13	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	322	1	0	0	0	0	1239	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29985	3	30011	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	3	0	0	5020	16	16	17	16	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	321	0	0	12	0	0	313	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29985	3	30011	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	1	0	0	0	0	5020	9	16	13	13	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	321	0	0	12	0	0	1007	25	160010	80010	80000	10	80085	50	640000	0	40019	40038	40038	29985	45	30750	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	2	3	0	0	5020	18	16	9	16	40035	80000	80010	40039	40039	40039	40039	40039
80024	40103	324	0	0	0	0	0	1498	43	160174	80010	80000	10	80000	50	640000	0	40019	40038	40038	29985	7	30011	80010	20	80000	20	80097	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	3	0	1	5020	15	16	13	8	40035	80079	80010	40039	40039	40039	40039	40039
80024	40105	331	0	0	9	0	0	708	25	160010	80089	80000	10	80000	50	640000	0	40019	40038	40038	29985	3	30011	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	1	0	0	0	0	5020	13	16	14	11	40035	80000	80010	40039	40039	40039	40039	40039

UMOV (B to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations