Firestorm: UMOV (D to X) measurements

Code:

  umov x0, v0.d[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	0	62	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	0	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	3	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	0	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	0	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	0	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	75	2	16	0	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	2	16	0	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	0	1	535	1000	1000	539	539	539	539	539
1004	538	5	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	1	0	75	1	16	0	1	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  umov x0, v0.d[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100038	775	0	0	3	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	2	0	0	1310	2	16	1	1	99639	10000	10000	10100	100039	100039	100039	100039	100039
20204	100116	775	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	527	4778577	5580349	1	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	2	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	3	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	12	0	0	100023	89568	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97497	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100040	100203	100039
20204	100038	775	0	0	0	0	0	21	0	0	100029	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778625	5580349	0	100013	100038	100038	96900	3	97497	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	6	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	18	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580407	0	100013	100038	100118	96900	3	97496	20224	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	0	0	1310	1	16	1	1	100038	10000	10000	10100	100039	100039	100473	100040	100039
20204	100038	775	0	0	0	0	2	0	0	0	100024	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100041	96900	3	97497	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100041	100042
20204	100038	776	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	16	2	1	99637	10000	10000	10100	100042	100042	100039	100039	100039
20204	100038	776	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	25	1	1	99637	10000	10000	10100	100039	100042	100039	100039	100039
20204	100117	776	0	0	0	1	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10050	500	4778481	5580349	1	100013	100038	100124	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100122	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	1	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10051	10050	500	4778481	5580349	0	100013	100038	100038	96900	3	97498	20100	200	10000	10123	208	10309	10247	100354	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10002	0	0	0	3	0	1310	2	16	3	1	99708	10000	10000	10100	100039	100039	100039	100039	100043

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3e	3f	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100038	776	0	0	0	0	0	0	0	100023	0	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	19	16	10	21	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100023	0	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	16	16	18	18	99637	10000	10000	10010	100039	100040	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100023	0	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100016	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	15	16	19	19	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100023	0	89563	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	18	16	19	18	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100023	0	89561	60	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	10	16	10	18	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	1	2	3	567	0	32	100023	36	89641	33	30010	10016	10000	10000	10	10000	10000	50	4778481	5579011	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100040	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	0	0	0	1270	19	16	18	19	99637	10000	10000	10010	100039	100039	100040	100039	100039
20024	100038	803	0	0	0	0	0	0	0	100107	0	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	0	100039	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1474	19	16	19	32	101481	10000	10000	10010	100044	100041	100040	100039	100041
20024	100045	803	0	0	0	0	24	0	0	100026	0	89561	25	30016	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10002	0	0	0	0	0	0	0	1270	19	16	11	19	99637	10000	10000	10010	100040	100039	100039	100039	100041
20024	100038	775	0	0	0	0	12	0	0	100108	0	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778625	5578954	100013	0	100038	100042	96922	3	97518	20010	20	10000	10000	20	10000	10000	100042	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	2	0	0	0	1	1	0	1270	19	16	19	18	99698	10004	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100177	0	89561	25	30018	10010	10000	10000	12	10000	10000	50	4778481	5578954	100013	0	100040	100041	96922	3	97518	20010	20	10066	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	0	0	0	1270	20	16	17	20	99637	10000	10000	10010	100039	100039	100039	100039	100039

Test 3: throughput

Count: 8

Code:

  umov x0, v8.d[1]
  umov x1, v8.d[1]
  umov x2, v8.d[1]
  umov x3, v8.d[1]
  umov x4, v8.d[1]
  umov x5, v8.d[1]
  umov x6, v8.d[1]
  umov x7, v8.d[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40053	300	0	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	0	0	0	0	1	697	25	160100	80100	80000	100	80004	500	640024	0	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	0	0	0	1	1	1	5119	0	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	3	0	1	1	1	5117	0	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	1	32	25	160100	80100	80000	100	80004	500	640024	1	40019	3	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	327	0	0	0	0	0	0	0	74	25	160100	80100	80000	100	80004	500	640024	1	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	0	120	25	160100	80100	80000	100	80004	500	640024	1	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80424	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	0	0	0	1	1	1	5117	0	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	1	32	25	160100	80100	80000	100	80004	500	640024	1	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	0	0	0	1	1	1	5117	0	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	0	697	25	160100	80100	80000	100	80004	500	640024	1	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	0	0	0	1	1	1	5117	0	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40108

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40047	310	1	1	2	2	174	232	512	62	160326	80093	80000	10	80000	50	640000	40179	40038	40038	29992	14	30018	80095	20	80000	20	80000	40038	40038	2	1	80021	10	9	10	80010	10	0	3	2	1	18	5020	1	16	0	0	0	7	1	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	323	0	0	0	0	1056	0	288	25	160010	80167	80000	10	80000	50	640000	40019	40038	40038	29992	3	30065	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	3	5020	1	16	0	0	0	2	1	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	325	0	0	0	0	21	0	331	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80089	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	1	9	5020	1	16	0	0	0	1	2	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	330	0	0	0	0	9	0	1207	25	160010	80010	80079	10	80000	50	640000	40019	40038	40038	29992	7	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	1	3	5020	1	16	0	0	0	1	1	40035	80000	80010	40039	40102	40039	40039	40039
80024	40038	321	0	0	0	0	0	0	1165	25	160010	80010	80000	10	80000	50	640000	40019	40038	40104	29992	3	30065	80010	20	80000	20	80000	40103	40038	2	1	80021	10	9	10	80010	10	0	0	0	1	3	5020	1	24	0	0	0	2	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	321	0	0	0	0	12	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80095	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	1	3	5020	1	16	0	0	0	2	2	40035	80000	80010	40106	40039	40039	40039	40039
80024	40038	325	0	0	0	0	9	0	151	25	160010	80010	80077	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	3	5020	1	16	127	0	3	2	2	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	321	0	0	0	0	0	0	130	25	160010	80010	80080	10	80000	50	640638	40019	40103	40038	29992	3	30018	80010	20	80000	20	80096	40038	40038	1	1	80021	10	9	10	80010	10	4	0	0	1	0	5020	1	16	0	0	1	1	1	40091	80000	80010	40039	40107	40104	40039	40039
80024	40038	324	0	0	0	0	12	0	413	25	160010	80010	80000	10	80088	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40103	1	1	80021	10	9	10	80010	10	4	2	0	1	3	5020	1	16	0	0	1	1	1	40035	80000	80010	40039	40039	40039	40039	40106
80024	40038	327	0	0	0	0	9	0	43	25	160010	80010	80000	10	80000	50	640000	40019	41384	41359	30514	109	30479	80179	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	1	3	5020	1	16	0	3	0	1	1	40035	80000	80010	40039	40039	40039	40039	40039

UMOV (D to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations