Firestorm: UMOV (H to W) measurements

Code:

  umov w0, v0.h[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	0	0	535	1000	1000	539	539	539	539	539
1004	538	4	9	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	0	0	535	1000	1000	539	539	539	539	539
1004	538	4	3	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	0	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	0	0	535	1000	1000	539	539	539	539	539
1004	538	4	3	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	0	0	535	1000	1000	539	539	539	539	539
1004	538	5	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	0	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	0	0	535	1000	1000	539	539	539	539	539
1004	538	5	0	85	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	0	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	86	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	0	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	0	0	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  umov w0, v0.h[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100125	806	1	0	8	8	939	616	0	100100	89562	25	30100	10100	10000	10000	117	10000	10000	500	4778481	5580349	0	100014	100124	100038	96900	3	97496	20100	200	10000	10059	200	10000	10000	100038	100038	2	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	2	16	1	1	99719	10000	10000	10100	100040	100039	100039	100113	100040
20204	100038	803	0	0	0	0	0	0	0	100023	89561	25	30116	10115	10007	10000	100	10000	10050	500	4778529	5580349	0	100013	100038	100038	96942	3	97554	20100	202	10000	10000	200	10000	10000	100124	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10002	0	0	100	0	0	0	1331	1	16	1	1	99638	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	804	0	0	1	0	147	0	0	100023	89561	25	30100	10100	10002	10000	100	10000	10000	500	4781060	5580349	0	100013	100038	100038	96902	3	97496	20220	200	10000	10059	200	10000	10000	100038	100038	2	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	16	1	1	99638	10000	10000	10100	100039	100039	100124	100039	100083
20204	100040	803	0	0	0	0	15	0	0	100023	89561	25	30100	10100	10003	10000	101	10000	10000	500	4780917	5580349	1	100013	100038	100038	96901	3	97496	20233	200	10000	10059	200	10000	10000	100039	100038	2	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	3	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100122	100039	100125
20204	100038	803	0	0	0	0	15	0	0	100026	89561	25	30100	10100	10002	10000	100	10000	10000	500	4778529	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10006	100038	100130	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100040	100220
20204	100038	803	0	0	0	0	30	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	519	4778481	5580349	0	100013	100038	100042	96952	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	1310	1	16	1	2	99637	10017	10000	10100	100039	100039	100039	100039	100042
20204	100038	804	0	0	0	0	15	0	0	100023	89563	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100015	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	1310	1	16	1	1	99638	10000	10000	10100	100042	100039	100039	100039	100043
20204	100299	807	1	1	7	3	795	440	0	100468	89786	136	30182	10131	10008	10004	111	10178	10000	521	4786446	5660697	0	100382	100463	100557	97132	32	97882	20785	206	10366	10374	208	10366	10368	100642	100546	8	1	20201	100	99	100	10100	10000	100	0	0	10000	2	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100042	100039	100041	100045
20204	100038	803	0	0	0	0	15	0	0	100023	89562	25	30100	10100	10000	10000	100	10000	10000	500	4779057	5580349	0	100014	100038	100038	96901	3	97496	20100	200	10000	10000	200	10000	10000	100040	100040	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	3	0	0	1	1310	1	16	1	1	99637	10000	10000	10100	100039	100040	100039	100044	100040
20204	100038	804	0	0	0	0	39	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778529	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100038	775	0	0	0	0	0	0	15	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5584459	0	100013	100038	100038	96923	3	97518	20012	20	10000	10000	20	10363	10000	100041	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	3	0	0	1272	10	16	10	10	99637	10002	10000	10010	100039	100042	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	0	100023	89561	44	30012	10012	10000	10000	12	10000	10000	60	4778464	5580149	0	100013	100038	100038	96922	3	97518	20012	20	10000	10061	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	3	2	0	1270	11	16	6	11	99637	10002	10000	10010	100039	100042	100039	100039	100039
20024	100038	775	1	0	0	0	0	0	132	0	0	100023	89561	25	30012	10012	10000	10000	10	10000	10000	60	4778464	5682769	0	100013	100038	100038	96922	3	97518	20012	20	10000	10000	20	10000	10000	100040	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	3	0	0	1272	10	16	11	11	99637	10002	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	1	0	0	0	0	0	0	0	0	100023	89562	25	30010	10010	10000	10000	12	10000	10000	60	4778481	5583576	0	100013	100038	100039	96922	3	97518	20012	20	10000	10000	20	10000	10000	100038	100127	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1272	6	16	9	9	99637	10000	10000	10010	100042	100039	100039	100039	100039
20024	100038	775	1	0	0	0	0	0	3	0	1	100023	89561	25	30012	10012	10000	10000	12	10000	10000	50	4778464	5583173	0	100013	100038	100038	96922	3	97518	20012	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	3	0	0	1270	9	16	11	10	99637	10002	10000	10010	100039	100041	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	0	100023	89561	25	30012	10012	10000	10000	12	10000	10000	55	4778481	5583554	0	100013	100038	100038	96922	3	97518	20012	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	1272	11	16	10	10	99637	10002	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	12	10000	10000	60	4778464	5581034	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100039	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	3	0	0	1272	12	16	12	10	99637	10004	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	1	0	0	0	0	0	0	0	0	100023	89561	25	30012	10010	10000	10000	12	10000	10000	55	4778464	5583647	0	100013	100038	100038	96961	3	97518	20012	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	3	0	0	1270	11	16	10	6	99637	10002	10000	10010	100039	100039	100125	100039	100039
20024	100038	775	0	0	0	0	0	0	12	0	0	100024	89561	45	30012	10012	10000	10000	12	10000	10000	60	4778464	5678284	0	100013	100039	100038	96922	3	97518	20010	20	10060	10000	20	10000	10000	100041	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1272	7	16	6	11	99637	10000	10000	10010	100047	100039	100039	100039	100039
20024	100038	775	1	0	0	0	0	0	12	0	0	100023	89561	25	30012	10012	10000	10002	12	10000	10000	60	4778464	5578954	0	100014	100038	100039	96922	3	97518	20012	20	10000	10000	20	10000	10000	100040	100118	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1272	13	16	11	11	99637	10002	10000	10010	100039	100039	100039	100039	100039

Test 3: throughput

Count: 8

Code:

  umov w0, v8.h[1]
  umov w1, v8.h[1]
  umov w2, v8.h[1]
  umov w3, v8.h[1]
  umov w4, v8.h[1]
  umov w5, v8.h[1]
  umov w6, v8.h[1]
  umov w7, v8.h[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40051	310	0	0	0	0	0	24	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	0	74	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	3	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	0	74	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80111	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	9	0	60	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	0	12	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	3	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	0	37	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	0	12	0	32	25	160100	80182	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	1	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40047	310	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	4	16	4	5	40035	80000	80010	40039	40039	40039	40106	40039
80024	40038	310	0	0	0	0	233	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	4	16	5	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	127	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80088	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	5	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	1	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40103	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	4	16	5	5	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	21	0	85	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	29992	8	30018	80010	20	80000	20	80000	40038	40038	2	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	5	16	6	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40103	29992	3	30018	80010	20	80089	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	580	0	0	5020	0	0	5	16	4	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	0	0	423	25	160010	80010	80000	10	80000	50	640000	0	0	40045	40038	40038	29992	3	30018	80098	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	5	16	5	5	40035	80000	80010	40039	40039	40105	40039	40039
80024	40038	310	0	0	0	0	43	25	160010	80010	80000	10	80087	50	640000	1	5	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	5	16	4	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	1	0	0	43	25	160010	80010	80000	10	80000	50	640670	0	0	40075	40038	40038	29992	3	30066	80010	20	80000	20	80000	40038	40038	2	1	80021	10	9	10	80010	10	0	0	0	0	0	560	0	0	5020	0	0	8	16	5	5	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	1	0	0	0	43	25	160010	80010	80000	10	80000	50	640686	0	0	40074	40105	40038	29992	3	30065	80010	20	80000	20	80000	40038	40105	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	5	16	3	5	40035	80000	80010	40039	40039	40039	40039	40105

UMOV (H to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations