Firestorm: UMOV (S to W) measurements

Code:

  umov w0, v0.s[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	c3	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	0	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  umov w0, v0.s[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100039	775	0	0	0	0	0	0	100023	89561	25	30125	10125	10000	10000	116	10000	10000	500	4778464	5678999	0	0	100013	0	100120	100038	96900	3	97495	20125	200	10000	10000	200	10000	10000	100038	100122	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	0	0	1312	0	0	2	17	2	4	99639	10025	0	10000	10100	100039	100039	100039	100039	100041
20204	100038	776	0	0	0	0	12	0	100023	89561	25	30100	10100	10000	10000	125	10000	10000	500	4778560	5679109	0	0	100013	0	100038	100038	96900	3	97495	20125	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	3	0	3	0	1312	0	0	1	17	2	2	99637	10025	0	10000	10100	100039	100039	100039	100039	100039
20204	100126	775	0	0	0	1	12	0	100027	89561	25	30125	10125	10000	10000	125	10000	10000	626	4778464	5682184	0	0	100013	0	100038	100038	96902	3	97495	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	0	0	1312	0	0	2	17	2	2	99637	10025	0	10000	10100	100041	100039	100117	100039	100040
20204	100038	776	0	0	0	0	0	0	100023	89563	42	30158	10125	10000	10000	125	10000	10000	626	4778464	5678999	0	0	100013	0	100038	100038	96900	3	97496	20125	202	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1312	0	0	3	16	1	3	99637	10025	0	10000	10100	100042	100039	100039	100039	100040
20204	100038	776	0	0	0	0	30	0	100023	89561	25	30125	10125	10000	10000	100	10056	10000	500	4778464	5679109	0	0	100013	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10374	102624	102635	33	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	1310	0	0	2	17	2	2	99637	10025	0	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	100023	89561	25	30125	10125	10000	10000	100	10000	10000	626	4778464	5678999	0	0	100013	0	100038	100038	96900	3	97495	20125	200	10000	10000	200	10000	10000	100038	100040	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	3	0	0	0	1312	0	0	2	17	2	3	99637	10025	0	10000	10100	100039	100041	100047	100042	100039
20204	100038	804	0	0	0	0	3	0	100023	89561	25	30125	10125	10000	10000	125	10000	10000	500	4778464	5678999	0	0	100013	0	100038	100038	96942	3	97495	20125	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	2	10000	0	1	0	0	0	1310	0	0	4	65	2	2	99637	10025	0	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	1	0	0	100023	89561	25	30125	10125	10000	10000	125	10000	10000	626	4778481	5580349	0	0	100013	0	100038	100122	96900	3	97496	20100	200	10000	10000	200	10000	10000	100039	100132	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3383	0	1312	0	0	1	25	3	2	99641	10025	0	10000	10100	100039	100040	100039	100040	100039
20204	100117	808	0	0	0	0	12	0	100023	89561	102	30125	10143	10031	10008	100	10000	10000	626	4778464	5679057	0	0	100016	0	100126	100038	96900	6	97495	20345	200	10000	10061	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10004	0	0	0	0	0	1312	5	4	2	17	2	2	99637	10025	0	10000	10100	100039	100042	100109	100081	100130
20204	100038	775	0	0	0	0	12	0	100023	89565	25	30133	10125	10000	10000	125	10000	10000	626	4778464	5678999	1	5	100013	0	100038	100038	97036	28	97979	20336	204	10120	10128	202	10123	11057	100715	100298	2	1	20202	100	99	100	10100	10000	100	2	2	10006	0	0	0	3460	0	1353	5	4	2	25	4	2	99784	10013	0	10000	10100	100207	100302	100215	100272	100302

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	77	dispatch uop (78)	79	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	inst barrier (9c)	9e	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cf	d0	d1	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100207	804	0	0	1	1	0	0	0	1	2	174	264	0	100102	89641	62	30018	10016	10005	10004	14	10175	10050	72	4780821	5665784	100158	0	100211	100202	96971	11	97638	0	20118	0	20	10121	10121	20	10061	10182	100122	100206	3	1	20021	10	9	10	10010	10000	0	0	10	0	0	10002	0	0	3355	0	7	0	1306	0	0	0	3	32	0	1	2	99842	0	10007	0	0	10000	10010	100304	100200	100208	100039	100041
20024	100038	804	0	0	0	0	0	0	0	0	0	12	0	0	100023	89564	25	30010	10010	10000	10000	10	10000	10000	77	4778817	5677969	102179	6	100038	100367	97469	109	98723	176	20010	28	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	356	10010	10000	1	3	10	0	0	10000	6	0	13495	108	0	0	1558	0	22	7	192	16	187	2	9	99728	14	10000	82	1	10000	10010	102120	100113	100096	102625	100208
20024	100157	804	1	10	0	6	0	0	44	0	0	1029	0	0	100023	89563	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579011	100094	0	100067	100038	96922	3	97521	0	20010	0	20	10000	10000	20	10000	10000	100039	100038	1	1	20021	10	9	10	10010	10000	0	0	10	0	0	10000	0	0	3	0	0	0	1270	0	0	0	1	16	0	1	1	99642	0	10000	0	0	10000	10010	100039	100039	100039	100040	100039
20024	100038	803	0	0	0	0	0	0	0	0	0	0	0	0	100023	89567	25	30010	10010	10000	10000	10	10000	10000	50	4778529	5579010	100013	0	100038	100039	96922	3	97518	0	20010	0	20	10000	10000	20	10000	10000	100038	100122	2	1	20021	10	9	10	10010	10000	0	0	10	0	0	10000	0	0	0	0	0	0	1270	0	0	0	1	16	0	2	1	99637	0	10000	0	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	0	24	0	0	100025	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778529	5578954	100013	0	100040	100038	96922	3	97518	0	20010	0	20	10000	10000	20	10000	10000	100038	100112	1	1	20021	10	9	10	10010	10000	0	0	10	0	0	10000	0	0	0	0	0	0	1270	0	0	0	1	16	0	1	1	99637	0	10000	0	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579122	100013	0	100038	100038	96922	3	97518	0	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	0	0	10	0	0	10000	0	0	0	0	0	2	1270	0	0	0	1	16	0	1	1	99637	0	10000	0	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	0	100038	100038	96922	3	97518	0	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	0	0	10	0	0	10000	0	0	0	0	0	0	1270	0	0	0	1	16	0	1	1	99637	0	10000	0	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	0	0	0	0	0	0	100026	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778577	5578954	100013	0	100038	100038	96922	3	97518	0	20010	0	20	10000	10000	20	10000	10000	100038	100101	1	1	20021	10	9	10	10010	10000	0	0	10	0	0	10000	1	0	0	0	0	0	1270	0	0	0	1	16	0	1	1	99637	0	10000	0	0	10000	10010	100040	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	0	100038	100038	96922	3	97518	0	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	0	0	10	0	0	10000	0	0	3	0	0	0	1270	0	0	0	1	16	0	1	1	99637	0	10000	0	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	0	100038	100038	96924	3	97518	0	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	0	0	10	0	0	10000	0	0	0	0	0	0	1270	0	0	0	1	16	0	1	1	99637	0	10000	0	0	10000	10010	100039	100039	100039	100039	100039

Test 3: throughput

Count: 8

Code:

  umov w0, v8.s[1]
  umov w1, v8.s[1]
  umov w2, v8.s[1]
  umov w3, v8.s[1]
  umov w4, v8.s[1]
  umov w5, v8.s[1]
  umov w6, v8.s[1]
  umov w7, v8.s[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40051	300	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80119	200	80111	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	5	16	5	5	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	6	16	2	4	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	246	132	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	6	16	6	6	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	6	16	6	6	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	6	16	6	6	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	299	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	4	16	2	4	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40104	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	5	16	6	6	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	1	6	1	1	1	5117	6	16	6	6	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	6	16	6	6	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	6	0	317	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	4	16	5	5	40035	80000	80100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	79	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40051	311	0	0	0	0	138	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	0	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	30	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	0	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	0	0	21	0	841	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	0	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	0	0	9	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	0	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	16	3	2	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	24	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	0	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	9	0	83	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	0	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	2	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	0	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	792	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	0	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640694	40073	40038	40038	29992	3	30018	80010	0	20	80000	20	80000	40038	40038	3	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	15	0	127	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	0	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039

UMOV (S to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations