Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

UMULL2 (by element, 4S)

Test 1: uops

Code:

  umull2 v0.4s, v0.8h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)03041e3a3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a8acc2cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
100430372300282254825100010001000398313030183037303724153289510001000200030373037111001100000077416442630100030383038303830383038
100430372310282254825100010001000398313030183037303724153289510001000200030373037111001100000077416442630100030383038303830383038
100430372310282254825100010001000398313130183037303724153289510001000200030373037111001100003077416442630100030383038303830383038
100430372210282254825100010001000398313030183037303724153289510001000200030373037111001100000077416442630100030383038303830383038
100430372310282254825100010001000398313030183037303724153289510001000200030373037111001100000477416442630100030383038303830383038
100430372210282254825100010001000398313030183037303724153289510001000200030373037111001100030077416442630100030383038303830383038
100430372200282254825100010001000398313030183037303724153289510001000200030373037111001100020077416442630100030383038303830383038
100430372210282254825100010001000398313030183037303724153289510001000200030373037111001100000077416442630100030383038303830383038
100430372210282254825100010001000398313030183037303724153289510001000200030373037111001100000077416442630100030383038303830383038
100430372310282254825100010001000398313030183037303724153289510001000200030373037111001100000077416442630100030383038303830383038

Test 2: Latency 1->2

Code:

  umull2 v0.4s, v0.8h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)03080b191e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a7a8acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372250008761295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250000612954825101251001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010020475071011611296340100001003003830038300383003830038
1020430037224000061295482510125100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000010071011611296340100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000060071011611296340100001003003830038300383003830038
1020430037224000061295482510125100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037225000061295482510125100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000010071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010021230710116112963425100001003003830038300383003830038
1020430037225000061295482510125100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000010071011611296340100001003003830038300383003830038
10204300372250000103295482510100100100001001000050042773130300183003730037282653287451026020010000200200003003730037111020110099100100100001000023071011611296340100001003003830038300383003830087
1020430037225000061295482510100100100001251000062642773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000019071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)031e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8a9accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1002430037225061295482510010101000010100005042773133001830037300372828703287671001020100002020000300373003711100211091010100001004015640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100200640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722505362954825100101010000101000050427731330018300373003728287032876710010201000020200003003730037111002110910101000010000141640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100003640216222963010000103003830038300383003830038
10024300372250126929548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100100640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  umull2 v0.4s, v1.8h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)0308090b18191e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ec? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372250010021061295482510100100100001001000050042773133001830037300372826572874510100200100002002000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
1020430037224000000061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
10204300372250000000822954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373008611102011009910010010000100000028060710119112963400100001003003830038300383003830038
1020530037225000000061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038
10204300372240000042061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000000000710116112963400100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)030b1e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a8acc2branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006404164429630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006406165629630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010013006406166629630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006406166629630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006406166629630010000103003830038300383003830038
1002430037225006062954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006405166629630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006405165629630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010209006406166529630010000103003830038300383003830038
100243003722500612954836100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006405165629630010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006404165529630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  umull2 v0.4s, v8.8h, v9.h[1]
  umull2 v1.4s, v8.8h, v9.h[1]
  umull2 v2.4s, v8.8h, v9.h[1]
  umull2 v3.4s, v8.8h, v9.h[1]
  umull2 v4.4s, v8.8h, v9.h[1]
  umull2 v5.4s, v8.8h, v9.h[1]
  umull2 v6.4s, v8.8h, v9.h[1]
  umull2 v7.4s, v8.8h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)03081e3f5051inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
802042006015000421200232580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000120511021611200360800001002004020040200402004020040
802042003915000410258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
8020420039150004102580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000093511011611200360800001002004020040200402004020040
802042003915000410258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000410258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000090511011611200360800001002004020040200402004020040
802042003915000410258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000410258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000410258010010080000100800005006400001200702003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000410258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000410258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000010511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)0308181e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8acc5cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
80024200481500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000050208161272003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050207165122003680000102004020040200402004020040
800242003915000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000502012165122003680000102004020040200402004020040
800242003915000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000502011165122003680000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010001305020416562003680000102004020040200402004020040
800242003915010040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000502011164102003680000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000005020516652003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050204165112003680000102004020040200402004020040
800242003915000092225800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050201116452003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050209165112003680000102004020040200402004020040