Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

UMULL2 (vector, 4S)

Test 1: uops

Code:

  umull2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)03071e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110009073216222630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000200030373037111001100010073216222630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110001073216222630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000200030373037111001100012283073216222630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000116820003037303711100110000073216222630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
1004303723006125482510001000100039831313018303730372417328951000100020003037303711100110000073216222630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
1004303722006125482510001000100039831313054303730372415328951000100020003037303711100110002073216222630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110004073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  umull2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)030b1e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9faccfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200101742002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250144612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250744612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)0309191e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
100243003722500031229548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006403162229630010000103003830038300383003830038
100243003722500017029548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100306402162229630010000103003830038300383003830038
100243003722500051829548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500048429548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722400012429548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500022529548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500018929548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722500023329548251001010100001410000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250008229548251001010100001010000504277313130018300373003728308328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  umull2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)031e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722507432954825101001161000010010000500427867003001830037300372826532874510100200100002002000030037300371110201100991001001000010002071011612296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722512612954825101001001000010010000500427731303001830037300372826582874510415200101672002000030037300371110201100991001001000010040071011611296340100001003003830038300383003830038
102043003722501032954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010001071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100001271011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510125200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10205300372250612954825101001001000010010000500427731313001830037300372826532874410100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)031e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9faccfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024300372250726295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830082
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006403162329632010000103003830038300383003830038
1002430037225061295482510010101000012101495042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001220100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001220100002020000300373003711100211091010100001006402162229630210000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001220100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250251295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250251295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  umull2 v0.4s, v8.8h, v9.8h
  umull2 v1.4s, v8.8h, v9.8h
  umull2 v2.4s, v8.8h, v9.8h
  umull2 v3.4s, v8.8h, v9.8h
  umull2 v4.4s, v8.8h, v9.8h
  umull2 v5.4s, v8.8h, v9.8h
  umull2 v6.4s, v8.8h, v9.8h
  umull2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)030b1e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a8cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
802042004915001205164780200124800981248010550064000012002020039200399973810023802252028010420016000020128200391180201100991001008000010000511021612200860800001002004020040200402004020040
8020420039150124041258010010080000100801035726400000200202003920039998239997801002008000020016000020039200391180201100991001008000010010511011611200360800001002004020040200402004020040
8020420039150030041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
8020420039150018041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915009041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
8020420039150054041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915006041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010001511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)031e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8accdcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
8002420039150270612580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000050201716652003680000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000005020616752003680000102004020040200402004020040
8002420039150004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100001502012165122003680000102004020040200402004020040
8002420039150004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000502012161272003680000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020160000200392011511800211091010800001000005020516642003680000102004020040200402004020040
8002420039150123040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000005020616542003680000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000005020516662003680000102004020040200402004020040
800242003915012040258001010800001080000506407561200202003920039999631001980010208000020160000200392003911800211091010800001000005020616662003680000102004020040200402004020040
800242003915027040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020516562003680000102004020040200402004020040
8002420039150035240258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020516642003680000102004020040200402004020040