Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

UMULL (by element, 4S)

Test 1: uops

Code:

  umull v0.4s, v0.4h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)03080b1e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
1004303723000822548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383074307430383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220001052548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110002073116112630100030383038303830383086
1004303722000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220001472548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  umull v0.4s, v0.4h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)03091e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8c5cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
102043003722400149295302510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372240061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500208295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500726295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500726295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500854295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101162129634100001003003830038300383003830038
102043003722500145295482510134100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)030818191e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1002430037225000001702954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000822954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000007262954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000001972954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000001242954825100101010000101000050427731303001833003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000001892954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000050006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  umull v0.4s, v1.4h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)030b191e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a7a8acc5cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372250002752954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300863003830038
10204300372250006792953925101001001000010010000500427731313001830037300372826532874510100204100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
10204300372250007262954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
10204300372250001242954825101001001001610010000500427731313001830037300372826532874510100200103322002000030037300371110201100991001001000010000160073413211296700100001003003830085300383003830085
10204300372251007262954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010041260071012511296670100001003003830038300383003830038
10204300372250002512954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000030071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)0308091e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8a9acc5cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
100243003722400061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216322963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100001200640216322963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216322963010000103003830038300383003830038
100243003722500061295394410010101000010100005042773130300183003730037282873287671001020100002020344300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001010000640216322963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216322963010000103003830038300383003830038
100243003722400061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722400061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216322963010000103003830038300383003830038
100243003722600061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  umull v0.4s, v8.4h, v9.h[1]
  umull v1.4s, v8.4h, v9.h[1]
  umull v2.4s, v8.4h, v9.h[1]
  umull v3.4s, v8.4h, v9.h[1]
  umull v4.4s, v8.4h, v9.h[1]
  umull v5.4s, v8.4h, v9.h[1]
  umull v6.4s, v8.4h, v9.h[1]
  umull v7.4s, v8.4h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)0318193f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9facbranch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
80204200581500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051103161220036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915000326258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161220036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200203200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)0308191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8accfd5d6d9ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
800242004815000048725800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109010108000010005020316102320036080000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109010108000010005020316103320036080000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110901010800001000502031683320036080000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110901010800001000502031662320036080000102004020040200402004020040
80024200391500007052580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110901010800001000502031663320036080000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110901010800001000502031663220036080000102004020040200402004020040
8002420039150000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110901010800001000502031663320036080000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110901010800001000502021662320036080000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110901010800001000502031663220036080000102004020040200402004020040
8002420039150000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110901010800001000502031663220036080000102004020040200402004020040