Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMULL (by element, 4S)

Test 1: uops

Code:

  umull v0.4s, v0.4h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723000822548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383074307430383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220001052548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110002073116112630100030383038303830383086
1004303722000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723000612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220001472548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  umull v0.4s, v0.4h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722400149295302510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372240061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500208295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500726295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500726295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500854295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101162129634100001003003830038300383003830038
102043003722500145295482510134100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000001702954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000822954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000007262954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000001972954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000001242954825100101010000101000050427731303001833003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000001892954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000050006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  umull v0.4s, v1.4h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250002752954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300863003830038
10204300372250006792953925101001001000010010000500427731313001830037300372826532874510100204100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
10204300372250007262954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
10204300372250001242954825101001001001610010000500427731313001830037300372826532874510100200103322002000030037300371110201100991001001000010000160073413211296700100001003003830085300383003830085
10204300372251007262954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010041260071012511296670100001003003830038300383003830038
10204300372250002512954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000030071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722400061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216322963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100001200640216322963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216322963010000103003830038300383003830038
100243003722500061295394410010101000010100005042773130300183003730037282873287671001020100002020344300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001010000640216322963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216322963010000103003830038300383003830038
100243003722400061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722400061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216322963010000103003830038300383003830038
100243003722600061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  umull v0.4s, v8.4h, v9.h[1]
  umull v1.4s, v8.4h, v9.h[1]
  umull v2.4s, v8.4h, v9.h[1]
  umull v3.4s, v8.4h, v9.h[1]
  umull v4.4s, v8.4h, v9.h[1]
  umull v5.4s, v8.4h, v9.h[1]
  umull v6.4s, v8.4h, v9.h[1]
  umull v7.4s, v8.4h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318193f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051103161220036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915000326258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161220036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200200200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
80204200391500041258010010080000100800005006400001200203200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000048725800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109010108000010005020316102320036080000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109010108000010005020316103320036080000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110901010800001000502031683320036080000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110901010800001000502031662320036080000102004020040200402004020040
80024200391500007052580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110901010800001000502031663320036080000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110901010800001000502031663220036080000102004020040200402004020040
8002420039150000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110901010800001000502031663320036080000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110901010800001000502021662320036080000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110901010800001000502031663220036080000102004020040200402004020040
8002420039150000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110901010800001000502031663220036080000102004020040200402004020040