Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

UMULL (vector, 4S)

Test 1: uops

Code:

  umull v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)031e1f3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a8a9accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
1004303722006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289510001000200030373037111001100000373116112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289510001000200030373037111001100000373116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  umull v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)031e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100071021622296340100001003003830038300383003830038
10204300372260612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100071021622296340100001003003830038300383003830038
102043003722505402954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100071021622296340100001003003830038300383008530038
10205300372250612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100071021622296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100071021622296340100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100071021622296340100001003003830038300383003830038
10204300712250612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100071021622296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100071021622296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001803003730037282650328745101002001000020020000300373003711102011009910010010000100071021622296340100001003003830038300383003830038
10204300372250612954825101001001000010010148500427731303001803003730037282650328745101002001000020020000300373003711102011009910010010000100071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)0307080a0b18191e1f3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a8acc2c5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024300372250000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100003006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313030018300373008428287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006424164429632010000103003830038300383003830038
10024300372250000003006129548251001010100001010000504277313030018300373003728287328767100122010000202000030037300371110021109101010000100200006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383008530038
100243003722500000000072629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006404162229630210000103003830038300383003830038
100243003722400000000053629548251001010100001010000504277313030018300373003728287328767100102010000202036030037300371110021109101010000100000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  umull v0.4s, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)03080b1e3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372250000387295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250000170295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250000170295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383008630038
1020430037225000061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250000210295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250000170295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250000191295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300813003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500001133295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250000170295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250000191295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)0307080a0b181e3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a8accdcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
100243003722510100021522954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000644101610102963010000103003830038300383003830038
10024300372251010002912954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000644101610102966810000103003830038300383003830038
10024300372241010002177295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000064481611112963010000103003830038300383003830038
1002430037225101000291295482510010101000010100005042767173001830037300372828732876710010201000020200003003730037111002110910101000010000064451610102963010000103003830038300383003830038
100243003722410100021332954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000644101611112963010000103003830038300383003830038
1002430037225101000291295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000064410161052963010000103003830038300383003830038
100243003722510100021122954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000644101611112963010000103003830038300383003830038
100243003722510100021332954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000644111610112963010000103003830038300383003830038
100243003722510100021122954825100101010000101000050427731330018300373003728287328767100102010000202000030037300371110021109101010000100000644101610112963010000103003830038300383003830038
1002430037225101000220029548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000006448168102963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  umull v0.4s, v8.4h, v9.4h
  umull v1.4s, v8.4h, v9.4h
  umull v2.4s, v8.4h, v9.4h
  umull v3.4s, v8.4h, v9.4h
  umull v4.4s, v8.4h, v9.4h
  umull v5.4s, v8.4h, v9.4h
  umull v6.4s, v8.4h, v9.4h
  umull v7.4s, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)033f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
802042005915141258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511051611200360800001002004020040200402004020040
802042003915041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915041448010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000514511611200360800001002004020040200402004020040
802042003915041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040
802042003915041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)03181e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a8acc2cfd0d5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
8002420048150000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000005020916161972003680000102004020040200402004020040
80024200391500001472580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000005020017167142003680000102004020040200402004020040
8002420039150000402580010108000010800005064000011200202003920039999631001980010208000020160000200392003911800211091010800001000325020017161782003680000102004020040200402004020040
800242003915000040258001010800001080000506400001120020200392003910015310019800102080000201600002003920039118002110910108000010000050203171617172003680000102004020040200402004020040
80024200391501604025800101080000138000050640000012002020039200399996310019800102080000201600002003920039118002110910108000010000050203171617172003680000102004020040200402004020040
8002420039150000402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000005020317161572003680000102004020040200402004020040
8002420039150000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000005020315168172003680000102004020040200402004020040
8002420039150000402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000005020317161762003680000102004020040200402004020040
80024200391503004025800101080000108000050640000002002020039200391001531001980010208000020160000200392003911800211091010800001003005020317161762003680000102004020040200402004020040
800242003915000264402580010108000010800005064000011200202003920039999631001980010208000020160000200392003911800211091010800001000005020317166172003680000102004020040200402004020040