Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQADD (vector, 4H)

Test 1: uops

Code:

  uqadd v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
1004303723126125482510001000100039831313018303730372415328951000100020003037303711100110000373216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqadd v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427779703001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225001242954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225001492954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225001452954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225001892954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225001662954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250027222954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225009872954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225002082954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225004352954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100013006402162229630010000103003830038300383003830038
1002430037224000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037224000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037224000000006129548251001010100001210000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001012100001010000604277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630210000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqadd v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000437101161129634100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372251102712954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000644101611529630010000103003830038300383003830038
100243003722511027629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006448168829630110000103003830038300383003830038
100243003722511027129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006441016101029630010000103003830038300383003830038
100243003722511027129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006441116101029630010000103003830038300383003830038
100243003722511027129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006441016101029630010000103003830038300383003830038
100243003722511027129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006441016101129630010000103003830038300383003830038
10024300372251102712954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010200644111610629630010000103003830038300383003830038
10024300372241102712954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000644101610629630010000103003830038300383003830038
100243003722511027129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006441016101029630010000103003830038300383003830038
100243003722411027129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006441016101029630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uqadd v0.4h, v8.4h, v9.4h
  uqadd v1.4h, v8.4h, v9.4h
  uqadd v2.4h, v8.4h, v9.4h
  uqadd v3.4h, v8.4h, v9.4h
  uqadd v4.4h, v8.4h, v9.4h
  uqadd v5.4h, v8.4h, v9.4h
  uqadd v6.4h, v8.4h, v9.4h
  uqadd v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150136258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051102161120036800001002004020040200402004020040
802042003915041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
802042003915041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
802042003915061258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051100161120036800001002004020040200402004020040
802042003915041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
8020420039150516258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
802042003914941258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
802042003915041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
80204200391504125801001008000010080000500640000020020200392003999731310025801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040
8020420039150231258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005026716242003680000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005020216442003680000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005020216242003680000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005020416622003680000102004020040200402004020040
800242003915006325800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000405024616422003680000102004020040200402004020040
8002420039150051525800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005020416242003680000102004020040200402004020040
800242003915006325800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005020216242003680000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050005020216242003680000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005020516422003680000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000005022216442003680000102004020040200402004020040