Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQADD (vector, 4S)

Test 1: uops

Code:

  uqadd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220612548251000100010003983131301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
10043037220612548251000100010003983130301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000033473116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000020073116112630100030383038303830383038
10043037220612548251000100010003983130301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqadd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722510126295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830085
102043003722500145295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383008130038
102043003722500124295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500145295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500124295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250082295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500166295482510100100100001001000050042773131300183003730037282653287451010020010000204200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500166295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500145295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500103295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225001186295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500151295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216212963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqadd v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722501542954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240842954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722501662954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722501452954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722501242954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722501662954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722400061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006612162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000571295482510010101000010101495042773130300543003730037282873287671030920101682020000300373022711100211091010100001002006402162229630010000103003830038300383003830038
100243003722500061295482510021111000811100005042773130300183003730037282913287671001020101672020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225001561295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722510061295482510010101000012100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000306402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000306612162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uqadd v0.4s, v8.4s, v9.4s
  uqadd v1.4s, v8.4s, v9.4s
  uqadd v2.4s, v8.4s, v9.4s
  uqadd v3.4s, v8.4s, v9.4s
  uqadd v4.4s, v8.4s, v9.4s
  uqadd v5.4s, v8.4s, v9.4s
  uqadd v6.4s, v8.4s, v9.4s
  uqadd v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004815005262580100100800001008000050064000012200202003920039997339997801002008000020016000020039200391180201100991001008000010002165110002161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000002200202003920039997339997801002008000020016000020039200391180201100991001008000010000005110001161120036800001002004020040200402004020040
80204200391500562580100100800001008000050064000010200202003920039997339997801002008000020016000020039200391180201100991001008000010000005110001161120036800001002004020040200402004020040
802042003915007062580100100800001008000050064000002200202003920039997339997801002008000020016000020039200391180201100991001008000010000005110001161120036800001002004020040200402004020040
8020420039150511252580100100800001008000050064000012200202003920039997339997801002008000020016000020039200391180201100991001008000010000005110201161120036800001002004020040200402004020040
80204200391500852580100100800001008000050064000012200202003920039997339997801002008000020016000020039200391180201100991001008000010040005110221161120036800001002004020040200402004020040
802042003915001252580100100800001008000050064000012200202003920039997339997801002008000020016000020039200391180201100991001008000010000005110221161120036800001002004020040200402004020040
802042003915004962580100100800001008000050064000012200202003920039997339997801002008000020016000020039200391180201100991001008000010000005110221161120036800001002004020040200402004020040
802042003915001292580100100800001008000050064000012200202003920039997339997801002008000020016000020039200391180201100991001008000010000005110201161120036800001002004020040200402004020040
802042003915001252580100100800001008000050064000012200202003920039997339997801002008000020016000020039200391180201100991001008000010000005110201161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150001052580010108000010800005064000005200202003920039999631001980010208000020160000200392003911800211091010800001000000502000616262003680000102004020040200402004020040
8002420039150008442580010108000012800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000000502000616442003680000102004020040200402004020040
800242003915000402580010108000010800005064000005200202003920039999631001980010208000020160000200392003911800211091010800001000000502002216242003680000102004020040200402004020040
8002420039150001242580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000000502000416242003680000102004020040200402004020040
800242003915000402580010108000010800005064000005200202003920039999631001980010208000020160000200392003911800211091010800001000000502000416422003680000102004020040200402004020040
800242003915000402580010108000010800005064000005200202003920039999631001980010208000020160000200392003911800211091010800001000100502000216242003680000102004020040200402004020040
8002420039150001052580010108000010801125064000005200202003920039999631001980010208000020160000200392003911800211091010800001000000502000216442003680000102004020040200402004020040
8002420039150009792580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000000503350216242003680000102004020040200402004020040
800242003915000402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000000502000416422003680000102004020040200402004020040
800242003915000822580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000000502000216242003680000102004020040200402004020040