Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQRSHL (scalar, D)

Test 1: uops

Code:

  uqrshl d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001162200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061253925100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000233630373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqrshl d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000274307101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300851110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007102161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010002007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000307101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000006406162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000006612162229630010000103003830038300383003830038
1002430037225000000053629548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000300006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300372110021109101010000100000000006402162229630010000103003830038300383003830038
100243003722400000006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504281384130018300373003728287328767100102010000202000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018300373003728287328786100102010000202000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqrshl d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225002110329548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100921073212511296700100001003003830038300383003830038
10204300372240006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500025129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000371011611296340100001003003830038300383003830038
102043003722511012429548651010010010000100100005004277313130018300373003728265328745102642001000020020322300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225001210329548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225011326129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001000290900640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001001000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uqrshl d0, d8, d9
  uqrshl d1, d8, d9
  uqrshl d2, d8, d9
  uqrshl d3, d8, d9
  uqrshl d4, d8, d9
  uqrshl d5, d8, d9
  uqrshl d6, d8, d9
  uqrshl d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500000005125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051102161120036800001002004020040200402004020040
8020420039150000000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000017151101161120036800001002004020040200402004020040
802042003915000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000009051101161120036800001002004020040200402004020040
80204200391500000004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
80204200391500000004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000020051101161120036800001002004020040200402004020040
802042003915000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000007251101161120036800001002004020040200402004020040
8020420039150000000622580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100000012951101161120036800001002004020040200402004020040
80204200391500000004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
80204200391500000004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000351101161120036800001002004020040200402004020040
80204200391500000004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000200051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815030402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100935020916642003680000102004020040200402004020040
8002420039150040258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010005020316352003680000102004020040200402004020040
8002420039150040258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010005020316552003680000102004020040200402004020040
8002420039150040818001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010005020616552003680000102004020040200402004020040
8002420039150040258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010005020616532003680000102004020040200402004020040
8002420039150040258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010005020416552003680000102004020040200402004020040
8002420039150040258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010005020516532003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002016000020039200391180021109101080000100455020616352003680000102004020040200402004020040
8002420039150040258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010005020316352003680000102004020040200402004020040
8002420039150040258001010800001080000506400002002020039200399996310019800102080000201600002003920039118002110910108000010205020316352003680000102004020040200402004020040