Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQRSHL (scalar, H)

Test 1: uops

Code:

  uqrshl h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073416112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372366125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqrshl h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000822954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500001702954825101001001000010010000500427731313001830037300372826532874510100200101662002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500005612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500003822954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500001032954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500001262954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500001262954825101001001000010010000500427731313001830037300372826532874510100204100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500001032954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722400004772954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0f18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225002000013372954825100101010000010100005042773130030018300373003728287328767100102010000202000030037300371110021109010101000010000000064002162229630010000103003830038300383003830038
100243003722500000008942954825100101010000010100005042773130030018300373003728287328767100102010000202000030037300371110021109010101000010000003064002162229630010000103003830038300383003830038
10024300372250000000612954825100101010000010100005042773130030018300373003728287328767100102010000202000030037300371110021109010101000010000000064002162229630010000103003830038300383003830038
10024300372240000000612954825100101010000010100005042773130030018300373003728287328767100102010000202000030037300371110021109010101000010000000064002162229630010000103003830038300383003830038
1002430037225000004860612954825100101010000010100005042773130030018300373003728287328767100102010000202000030037300371110021109010101000010000000064002162229630010000103003830038300383003830038
10024300372250000000612954825100101010000010100005042773130030018300373003728287328767100102010000202000030037300371110021109010101000010000000064002162229630010000103003830038300383003830038
10024300372250000000612954825100101010000010100005042773130030018300373003728287328767100102010000202000030037300371110021109010101000010000000064002162229630010000103003830038300383003830038
10024300372250000000612954825100101010000010100005042773130030018300373003728287328767100102010000202000030037300371110021109010101000010000000064002162229630010000103003830038300383003830038
10024300372250000000612954825100101010000010100005042773130030018300373003728287328767100102010000202000030037300371110021109010101000010000000064002162229630010000103003830038300383003830038
10024300372250000000612954825100101010000010100005042773130030018300373003728287328767100102010000202000030037300371110021109010101000010000000064002162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqrshl h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)181e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000812954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722500000992954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
1020430037225000007262954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
1020430037225000006312954825101001001000010210000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
1020430037225000007262954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001012100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225008429548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uqrshl h0, h8, h9
  uqrshl h1, h8, h9
  uqrshl h2, h8, h9
  uqrshl h3, h8, h9
  uqrshl h4, h8, h9
  uqrshl h5, h8, h9
  uqrshl h6, h8, h9
  uqrshl h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150014103025801081008000810080020500640132200202003920039997769990801202008003220016006420039200391180201100991001008000010000111511821600200360800001002004020040200402004020040
80204200391500003025801081008000810080020500640132200202003920039997769990801202008003220016006420039200391180201100991001008000010000111511801600200360800001002004020040200402004020040
80204200391500004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915001804125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
80204200391500004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
8020420039150051904125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915002704125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511021611200360800001002004020040200402004020040
80204200391500004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
80204200391500004125801001008000010080116500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915001504125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd2l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000001500402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000000050200020167520036080000102004020040200402004020040
800242003915000000000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000000050200011167520036080000102004020040200402004020040
800242003915000000000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000000050200061671020036080000102004020040200402004020040
800242003915000000000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000000050200061661020036080000102004020040200402004020040
80024200391500000090040258001010800001080000506400000200202003920039999631001980010208000020160000200932008911800211091010800001000000005020008167520036080000102004020040200402004020040
800242003915000100000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000000050200011168920036080000102004020040200402004020040
800242003915100000150040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000005020006165820036080000102004020040200402004020040
80024200391500000000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000005020006169520036080000102004020040200402004020040
80024200391500000000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000000005020008168620036080000102004020040200402004020040
80024200391500000000040258001010800001080000506400000200202003920039999631010080010208000020160000200392003911800211091010800001000000005020006167720036080000102004020040200402004020040