Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQRSHL (vector, 4H)

Test 1: uops

Code:

  uqrshl v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)91inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037234261254825100010001000398313301830373037241532895100010002000303730371110010100073216222630100030383038303830383038
10043037220236254825100010001000398313301830373037241532895100010002000303730371110010100073216222630100030383038303830383038
10043037220103254825100010001000398313301830373037241532895100010002000303730371110010100073216222630100030383038303830383038
1004303722061254825100010001000398313301830373037241532895100010002000303730371110010100073216222630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010002000303730371110010100073216222630100030383038303830383038
1004303722061254825100010001000398313301830373037241532895100010002000303730371110010100073216222630100030383038303830383038
10043037230230254825100010001000398313301830373037241532895100010002000303730371110010100073216222630100030383038303830383038
1004303723061254825100010001000398313301830373037241532895100010002000303730371110010100073216222630100030383038303830383038
1004303722061254825100010001000398313301830373037241532895100010002000303730371110010100073216222630100030383038303830383038
10043037220373254825100010001000398313301830373037241532895100010002000303730371110010100073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqrshl v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372251006129548251010010010000100100005004277313030018300373003728265328745101002021000020020000300373003711102011009910010010000100101597101161129634100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010010217101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000787101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000787101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030084300371110201100991001001000010000847101161129634100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000907101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000127101161129634100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000667101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000667101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225012612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010130640216222963010000103003830038300383003830038
1002430037225012612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010100640216222963010000103003830038300383003830038
1002430037225001032954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010002640216222963010000103003830038300383003830038
1002430037225024612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqrshl v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372242061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001003071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300842826503287451010020010000200200003003730037111020110099100100100001003071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037211020110099100100100001001071011611296340100001003003830038300383003830086
1020430037225006129548251010010010000100100005004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100531271011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000371011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001002071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001001071011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001001071011611296340100001003003830038300383003830233
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001001071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265032874510100200100002002000030037300371110201100991001001000010037071011611296910100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500822954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225008229548251001010100001010000504277313030018030037300372828732876710010201000020200003003730037111002110910101000010024006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010027006402162229630010000103003830038300383003830038
1002430037225007629548251001010100001010000504277313030018030037300372828732876710010201000020200003003730037111002110910101000010030006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010024006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018030037300372828732876710010201000020200003003730037111002110910101000010027006402162229630010000103003830038300383003830038
100243003722400612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430085225006129548251001010100001010000504277313030018030037300372828732876710010201000020200003003730037111002110910101000010021006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313030018030037300372828732876710010201000020200003003730037111002110910101000010018006402162229630010000103003830038300383003830038
1002430037224006129548251001010100001010000504277313030018030037300372828732876710010201000020200003003730037111002110910101000010030006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uqrshl v0.4h, v8.4h, v9.4h
  uqrshl v1.4h, v8.4h, v9.4h
  uqrshl v2.4h, v8.4h, v9.4h
  uqrshl v3.4h, v8.4h, v9.4h
  uqrshl v4.4h, v8.4h, v9.4h
  uqrshl v5.4h, v8.4h, v9.4h
  uqrshl v6.4h, v8.4h, v9.4h
  uqrshl v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815000000004125801001008000010080000500640000120020200392003999730399978010020080000200160000200392003911802011009910010080000100000000870000511021611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000002002020039200399973039997801002008000020016000020039200391180201100991001008000010000000000000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000012002020039200399973039997801002008000020016000020039200391180201100991001008000010000001090000511011611200360800001002004020040200402004020040
80204200391550000000412580100100800001008000050064000012002020039200399973039997801002008000020016000020039200391180201100991001008000010000001090000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000012002020039200399973039997801002008000020016000020039200391180201100991001008000010000001030000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000012008520039200399973039997801002008000020016000020039200391180201100991001008000010000000060000511011611200360800001002004020040200402004020040
802042003915000000004125801001008000010080000500640000120020200392003999730399978010020080000200160000200392003911802011009910010080000100000000625000051101282112007918800001002009820102200912009020040
8020420039150000000041478021312380000118800985006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000001470000511011611200360800001002004020040200402004020040
80204200391500000000412580100100800001008000050064000002002020039200399973031002480100200800002001600002003920039118020110099100100800001000000001112000511011611200360800001002004020040200402004020040
802042003915000006004125801001008000010080000500640000120020200392003999730399978010020080000200160000200392003911802011009910010080000100000000780000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000822580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010093502001160112003680000102004020040200402004020040
8002420039150012402580090108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010469502001160112003680000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000201604202003920140118002110910108000010027502001160112003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010093502001160112003680000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000502001160112003680000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000502001160112003680000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010590502001160112003680000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000502001160112003680000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000502001160112003680000102004020040200402004020040
80024200391500040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001013502041160112003680000102004020040200402004020040