Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQRSHL (vector, 8B)

Test 1: uops

Code:

  uqrshl v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372200061254825100010001000398313130543037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372300061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372200061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723001261254825100010001000398313130183037303724153289510001000233630373037111001100000073116112630100030383038303830383038
100430372300061254825100010001000398313130183037303724153289510001000200030373037111001100000280073116112630100030383038303830383038
1004303722000612548251008100010003983131301830373037241532895100010002000303730371110011000007273116112630100030383038303830383038
1004303723000612548251000100010003983131301830373037241532895100010002000303730371110011000007273116112630100030383038303830383038
100430372200061254825100010001000398313130183037303724153289510001000200030373037111001100000673116112630100030383038303830383038
100430372300061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723000612548251000100010003983131301830373037241532895100010002000303730371110011000002773116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqrshl v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000018929548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722500000095029548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250000001582295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000100007101161129634100001003003830038300383003830038
102043003722500000097029548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722500000096929548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372240000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250000008229548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225000000103829548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
10204300372250000150109629548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
102043003722500000095129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007101171129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250011782954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222970210000103003830038300383003830038
10024300372250010772954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225008862954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225008732954825100101010000101000060427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037224001102295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000144640216222963010000103003830038300383003830038
10024300372250011852954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383008530038
10024300372250012402954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372240011242954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250010552954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqrshl v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000028729548251010010010000100100005004277313300180300373003728265328745101002001000020020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038
10204300372240000000098529548251010010010000100100005004277313300180300373003728265328745101002001000020020000300373003711102011009910010010000100220030229000982172422999538100001003003830038300383003830038
1020430037233011121311881144083962948420210213151101041531104381342867753027003051530658282914628877119522381116522824294305633037310110201100991001001000010020200238000200710116112963430100001003041830421305653037330323
10204303752350011012924704173522947623810215152100881281104378742866973023403065930706282986828928121002281216324823970305493065714110201100991001001000010020001233520000914196233001837100001003051730420307023050430276
1020430514238011000001452954825101001001000010010000500427731330018030037300372826532876110100200100002002000030037300371110201100991001001000010022210031535000733297223007029100001003003830038300383003830038
1020430370235001141115846160772029548251010010810000100100005004277313300180300373003728265328745101002001000020020000300373003711102011009910010010000100000000300071011611296340100001003003830038300383003830038
10204300372330000000028329548251010010010000100100005004277313300180300373003728265328745101002001000020020000300843003711102011009910010010000100000000000071011611296340100001003003830038300383003830038
1020430037225000000008429548251010010010000100100005004277313300180300373003728265328745101002001000020020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038
10204300372250000000021229548251010010010000100100005004277313300180300373003728265328745101002001000020020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038
10204300372250000000033229548251010010010000100100005004277313300180300373003728265328745101002001000020020000300373003711102011009910010010000100000000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722512900145295482510010101000010100005542773130300543003730037282873287671015920103302020000300373008421100211091010100001010640216222963010000103003830038300383003830038
1002430037225000298295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001006640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250108061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225000103295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001003640216222963010000103003830038300383003830038
1002430037225120061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372251200103295482510010101000810100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001003640216222963010000103003830038300843003830038

Test 4: throughput

Count: 8

Code:

  uqrshl v0.8b, v8.8b, v9.8b
  uqrshl v1.8b, v8.8b, v9.8b
  uqrshl v2.8b, v8.8b, v9.8b
  uqrshl v3.8b, v8.8b, v9.8b
  uqrshl v4.8b, v8.8b, v9.8b
  uqrshl v5.8b, v8.8b, v9.8b
  uqrshl v6.8b, v8.8b, v9.8b
  uqrshl v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420048150319225801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051102161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001002051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
8020420039150061125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161220036800001002004020040200402004020097
802042003915004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000020020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040
8020420039150013625801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)daddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481501402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000050200301601526200360080000102004020040200402004020040
800242003915001282580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000050200261601627200360080000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000050200281602725200360080000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000050200271602727200360080000102004020040200402004020040
800242003915005822580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000050200271602127200360080000102004020040200402004020040
800242003915006252580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000050200271602627200360080000102004020040200402004020040
80024200391500402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000050200271602127200360080000102004020040200402004020040
800242003915005022580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000050200261602828200360080000102004020040200402004020040
8002420039157036225800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000104400050200281602828200360080000102004020040200402004020040
80024200391500402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000050200151602720200360080000102004020040200402004020040