Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQRSHL (vector, 8H)

Test 1: uops

Code:

  uqrshl v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110001073316332630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073316232630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110001373316332630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
100430372316125482510001000100039831303018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073316232630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
1004303722061254825100010001000398313030183037303724153289510001000200030373037111001100033073316232630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqrshl v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372256129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372256129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372256129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372256129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372256129548251010010010000100100005004277313130018300373018128265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722572629548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372256129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372256129530251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372246129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372246129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000006129548251001010100001010000504277313130018300373003728287032876710010201000020200003003730037111002110910101000010000080550906402162229630010000103003830180300383003830038
100243003722500000010329548251001010100001010000504277313130018301323003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313130018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722400000012629548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372240000006129548251001010100001010000504277313130018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018300373003728287032876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000105295482510010101000010100005042773130300183003730037282870328806110562410988222227430132303248110021109101010000102430121953027664854229884410000103016930368303223037030358

Test 3: Latency 1->3

Code:

  uqrshl v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500400010329548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000471011611296340100001003003830038302283003830038
10204300372250000006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004278675300183003730037282653287451010020010000200200003003730037411020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313300183003730037282743287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250000008229548251010010010016100100005004277313300183003730037282653287451010020010000200200003022830037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037225000000148829548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000200071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003722500400024429548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000090071011611296340100001003003830038300383003830038
10204300372240000006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000102000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100090640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300180300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005542773130300180300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722501261295482510010101000010100005042786700300180300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500360295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300180300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183300373003728287328767100102010000202000030037300371110021109101010000100001640216222963010000103003830038300383003830038
10024300372330061295482510010101000010100005042773131300180300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uqrshl v0.8h, v8.8h, v9.8h
  uqrshl v1.8h, v8.8h, v9.8h
  uqrshl v2.8h, v8.8h, v9.8h
  uqrshl v3.8h, v8.8h, v9.8h
  uqrshl v4.8h, v8.8h, v9.8h
  uqrshl v5.8h, v8.8h, v9.8h
  uqrshl v6.8h, v8.8h, v9.8h
  uqrshl v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150390412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051102161120036800001002004020040200402004020040
8020420039150840412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391501410412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150150412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150242641082580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
80204200391505190412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000050202316952003680000102004020040200402004020040
80024200391500000154025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000050206167102003680000102004020040200402004020040
80024200391500000340258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000005235020916472003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000050206166102003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000050205167102003680000102004020040200402004020040
800242003914900000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000005020816682003680000102004020040200402004020040
800242003915000000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000005020716882003680000102004020040200402004020040
8002420039150000099402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000005020816692003680000102004020040200402004020040
800242003915000000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000005020516682003680000102004020040200402004020040
800242003915000000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000005020716832003680000102004020040200402004020040