Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQRSHRN2 (2D)

Test 1: uops

Code:

  uqrshrn2 v0.4s, v1.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723006125482510001000100039831330223037303724153289510001000200030373037111001100000073316112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037221206125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037221206125482510001000114939831330183037303724153289510001000200030373037111001100001073116112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289510001000200030373037111001100000094116112630100030383038303830383038
1004303722006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723006125482510001000100039831330183037303724153289511491000200030373037111001100000073116112630100030383038303830383038
1004303722006125482510001000100039831330183037303724153289510001000200030373037111001100000275573116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  uqrshrn2 v0.4s, v1.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000008642954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000300071011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
10204300372250000001702954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
10204300372250000001282953944101251001000812810000500428002713001830037300372826532874510100200100002022000030037300371110201100991001001000010000002303071011611297010100001003008630038300863012330038
1020430037225000000126295392510100100100001001000050042773131300183003730037282653287451010020010000200203343003730037111020110099100100100001000000019470865373232990232100001003037130372303713032430323
102043036922711779246165666294851651019714810056139104477394286775130270300853037128290362887210254222113302262263830371301808110201100991001001000010020200251358692105122998032100001003046530467304683042230323
10204304192281192118870452092947618210222143100641451134169542880171303063046830467283054628892114282161132222722988304663045610110201100991001001000010000010071011611296340100001003003830038300383003830038
10204300372240000001072954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225000000612954825101001001000010010000500427731313001830037300372826532874510228200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006403242229630010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773131300183003730037282873287671001020100002020322300853008511100211091010100001000006402162229630010000103003830038300383003830038
10024300372250000536295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830180
1002430037224000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000084295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225006061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  uqrshrn2 v0.4s, v0.2d, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722506129547251010010010000100100005004277160300183003730037282716287411010020010008200200163003730037111020110099100100100001000011171816296450100001003003830038300383003830038
1020430037225087429547251010010010000100100005004277160300183003730037282717287401010020010008200200163003730037111020110099100100100001000011171716296450100001003003830038300383003830038
1020430037225012629547251010010010000100100005004277160300183003730037282717287401010020010008200200163003730037111020110099100100100001000011171716296460100001003003830038300383003830038
1020430037225126129547251010010010000100100005224277160300903008430037282757287411010020010008200200163003730037111020110099100100100001001287311171816296460100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160300183003730037282716287401010020010008200200163003730037111020110099100100100001000011171816296450100001003003830038300383003830038
1020430037225010329547251010010010000100100005004277160300183003730037282716287401010020010008200200163003730037111020110099100100100001000011171716296452100001003003830038300383003830038
1020430037225128229547251010010010000100100005004277160300183003730037282717287401010020010008200200163003730037111020110099100100100001000011171716296450100001003003830038300383003830038
102043003722508229547251010010010000100100005004277160300183003730037282717287401010020010008200200163003730037111020110099100100100001002011171716296450100001003003830038300383003830038
10204300372241293529547251010010010000100100005004277160300183003730037282717287401010020010008200200163003730037111020110099100100100001000011171816296450100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160300183003730037282716287411010020010008200200163003730037111020110099100100100001000011171816296460100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500200295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020324300373003711100211091010100001000640216222962910000103003830038300383003830038
100243003722500103295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
100243003722500170295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
100243003722500145295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000640216222962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uqrshrn2 v0.4s, v8.2d, #3
  movi v1.16b, 0
  uqrshrn2 v1.4s, v8.2d, #3
  movi v2.16b, 0
  uqrshrn2 v2.4s, v8.2d, #3
  movi v3.16b, 0
  uqrshrn2 v3.4s, v8.2d, #3
  movi v4.16b, 0
  uqrshrn2 v4.4s, v8.2d, #3
  movi v5.16b, 0
  uqrshrn2 v5.4s, v8.2d, #3
  movi v6.16b, 0
  uqrshrn2 v6.4s, v8.2d, #3
  movi v7.16b, 0
  uqrshrn2 v7.4s, v8.2d, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2509

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420090150000000050258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011901600200621600001002006620066200662006620066
16020420065150000000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011901600200621600001002006620066200662006620066
16020420065150000000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011901600200621600001002006620066200662006620066
16020420065150000000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011901600200621600001002006620066200662006620066
16020420065150000000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011901600200621600001002006620066200662006620066
16020420065150000000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011901600200621600001002006620066200662006620066
16020420065150000000029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011901600200621600001002006620066200662006620066
16020420065150000000052258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011901600200621600001002006620066200662006620066
160204200651500000000694258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011901600200621600001002006620066200662006620066
16020420065150000000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011901600200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200651500000004525800101080000108000050640000115200272004620046322800102080000201600002004620046111600211091010160000100000001003282192021110920043150160000102004720047200472004720047
1600242004615000000045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000000010031821112021191120043150160000102004720047200472004720047
16002420046150000000452580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010000000100338211020211111120043150160000102004720047200472004720047
160024200461500000008725800101080000108000050640000115200272004620046322800102080106201600002004620046111600211091010160000100120001003282192021191120043150160000102004720047200472004720047
1600242004615000000073258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000000010034821122021110920043150160000102004720047200472004720047
1600242004615000000045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000000010032821920211101120043150160000102004720047200472004720047
16002420046150000000662580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010000000100348219202119820043150160000102004720047200472004720047
16002420046150000000452580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010000000100348211220211111120043150160000102004720047200472004720047
16002420046150000000452580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010000000100338211020211111020043150160000102004720047200472004720047
160024200461500000004525800101080000108000050640000115200272004620046322800102080000201600002004620046111600211091010160000100000001003382192021111920043150160000102004720047200472004720047

Test 5: throughput

Count: 16

Code:

  uqrshrn2 v0.4s, v16.2d, #3
  uqrshrn2 v1.4s, v16.2d, #3
  uqrshrn2 v2.4s, v16.2d, #3
  uqrshrn2 v3.4s, v16.2d, #3
  uqrshrn2 v4.4s, v16.2d, #3
  uqrshrn2 v5.4s, v16.2d, #3
  uqrshrn2 v6.4s, v16.2d, #3
  uqrshrn2 v7.4s, v16.2d, #3
  uqrshrn2 v8.4s, v16.2d, #3
  uqrshrn2 v9.4s, v16.2d, #3
  uqrshrn2 v10.4s, v16.2d, #3
  uqrshrn2 v11.4s, v16.2d, #3
  uqrshrn2 v12.4s, v16.2d, #3
  uqrshrn2 v13.4s, v16.2d, #3
  uqrshrn2 v14.4s, v16.2d, #3
  uqrshrn2 v15.4s, v16.2d, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440059300000179261601161001600161001600285001280196040029400494004819976101998616012820016003820032007640049400491116020110099100100160000100000002221012922311400461600001004005040049400494004940050
160204400493000006427160116100160016100160028500128019604002940048401211997691998616012820016003820032007640049400491116020110099100100160000100000002221012812311400451600001004005040050400504004940049
160204400493000006426160116100160016100160028500128019604002940048400481997691998616012820016003820032007640048400491116020110099100100160000100000002221012912311400451600001004004940050400494004940049
16020440048300000642716011610016001610016002850012801960400294004940048199769200141603312001601432003200764004840098111602011009910010016000010023029402221012812311400451600001004051140677405154062440257
1602044004930011041826160406100160016100160028500128019614002940049400491997691998616012820016014320032007640048400481116020110099100100160000100000002221012812311400451600001004005040050400504004940050
160204400483000006427160116100160016100160028500128019614002940049400481997691998616012820016003820032007640048400481116020110099100100160000100000002221012812311400451600001004004940049400494004940050
160204400483000006426160116100160016100160028500128019604002940113400481997691998616012820016003820032007640048400481116020110099100100160000100000002221012812311400451600001004004940049400494005040049
1602044004830000064261601161001600161001600285001280196140029400494004819976919986160128200160038200320076400484004811160201100991001001600001000000332221012812311400461600001004004940049400504005040049
160204400483000006426160116100160016100160028500128019614002940048400481997691998616012820016003820032007640048400491116020110099100100160000100000002221012912311400451600001004004940049400494004940049
1602044004830000064451602131001600161001600285001280196040070401514004819976141998616012820016003820032007640048400491116020110099100100160000100000002221016212321400881600001004004940049400494005040050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)branch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244005130010000012011692516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940040111600211091010160000100001002480104116111172940036165160000104004040040400404004040040
160024401423001010001200992516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940039111600211091010160000100001002284106016111222740036165160000104004040040400404004040040
16002440039300101000000992516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940039111600211091010160000100001002484111616311192940036165160000104004040040400404004040151
1600244015130010112226417614946516020510160195101602125012816201154002040039400391999632001916001020160000203200004003940039111600211091010160000100001002484113016311293040036165160000104004040040400404004040040
160024400393001010000007582516001010160000101600005012800001154002040039400391999632001916003420160000203200004003940039111600211091010160000100101002384112516311242440036165160000104004040040400404004040040
160024400393001010000009325160010101600001016000050128000001540020400394003919996320019160010201600002032000040099400391116002110910101600001000010026115112016311282440036165160000104004040040400404004040040
1600244003930010100000193251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000100231151126163112525400361610160000104004040040400404004040040
160024400393001010001201992516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940039111600211091010160000100001002384112616122262540036315160000104004040040400404004040040
16002440039300101000000932516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940039111600211091010160000100001002485112716321252840036165160000104004040040400404004040040
16002440039300101000001932516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940039111600211091010160000100001002385112716111262640118165160000104004040040400404004040040