Firestorm: UQRSHRN2 (8H) measurements

Code:

  uqrshrn2 v0.16b, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	6	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	6	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	103	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	6	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	12	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  uqrshrn2 v0.16b, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	46	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	5	2853	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30229	225	0	0	61	29537	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	6	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	78	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30232	225	1	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	710	2	16	2	2	29634	1	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	90	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	278	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	12	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	278	0	0	0	0	0	84	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	6	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	280	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	78	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	260	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	260	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	260	0	0	0	12	0	103	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	0	0	747	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	12	0	145	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	15	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	0	0	342	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	6	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	0	0	696	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  uqrshrn2 v0.16b, v0.8h, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	3	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30228
10204	30037	224	0	0	12	0	1	97	29547	25	10100	100	10000	100	10000	549	4277160	30018	30037	30037	28252	6	28733	10406	214	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	11097	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	1	97	29547	25	10100	100	10008	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	722	2	24	2	2	29629	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	12	0	1	97	29547	25	10100	100	10000	100	10000	500	4278512	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30227	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30227	225	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30229
10204	30037	225	0	0	9	176	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	198	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	251	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	2	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30054	30037	30037	28286	3	28767	10010	20	10000	20	20344	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	84	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	66	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	82	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	114	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28786	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uqrshrn2 v0.16b, v8.8h, #3
  movi v1.16b, 0
  uqrshrn2 v1.16b, v8.8h, #3
  movi v2.16b, 0
  uqrshrn2 v2.16b, v8.8h, #3
  movi v3.16b, 0
  uqrshrn2 v3.16b, v8.8h, #3
  movi v4.16b, 0
  uqrshrn2 v4.16b, v8.8h, #3
  movi v5.16b, 0
  uqrshrn2 v5.16b, v8.8h, #3
  movi v6.16b, 0
  uqrshrn2 v6.16b, v8.8h, #3
  movi v7.16b, 0
  uqrshrn2 v7.16b, v8.8h, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	0	111	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	493	1	1	1	10119	1	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	60	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	1	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80327	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	2	0	0	1	1	1	10119	0	16	0	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80124	100	80028	500	640196	1	20045	20065	20065	20	12	80128	200	80346	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	1	57	0	0	20138	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	24	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20097	150	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10043	8	1	1	19	25	2	1	1	20	8	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20060	150	387	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10043	8	2	1	19	25	2	1	1	20	8	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	151	381	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20060	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10043	8	2	1	19	25	2	1	1	20	20	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10031	8	2	1	9	34	2	1	1	20	9	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	51	27	80010	10	80000	10	80000	50	640000	0	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10040	8	3	1	19	25	2	1	1	19	9	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10034	8	2	1	9	25	2	1	1	7	19	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	231	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	5	0	2	720	10043	8	2	1	19	25	2	1	1	19	19	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10034	8	2	1	9	25	2	1	1	9	19	20048	20	1	160000	10	20052	20052	20052	20052	20061
160024	20051	150	30	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10031	8	2	1	9	25	2	1	2	19	9	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20051	150	201	0	45	27	80010	10	80000	10	80000	50	640000	1	1	5	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	8	2	1	9	25	2	1	1	19	9	20048	20	1	160000	10	20052	20052	20052	20052	20052

Test 5: throughput

Count: 16

Code:

  uqrshrn2 v0.16b, v16.8h, #3
  uqrshrn2 v1.16b, v16.8h, #3
  uqrshrn2 v2.16b, v16.8h, #3
  uqrshrn2 v3.16b, v16.8h, #3
  uqrshrn2 v4.16b, v16.8h, #3
  uqrshrn2 v5.16b, v16.8h, #3
  uqrshrn2 v6.16b, v16.8h, #3
  uqrshrn2 v7.16b, v16.8h, #3
  uqrshrn2 v8.16b, v16.8h, #3
  uqrshrn2 v9.16b, v16.8h, #3
  uqrshrn2 v10.16b, v16.8h, #3
  uqrshrn2 v11.16b, v16.8h, #3
  uqrshrn2 v12.16b, v16.8h, #3
  uqrshrn2 v13.16b, v16.8h, #3
  uqrshrn2 v14.16b, v16.8h, #3
  uqrshrn2 v15.16b, v16.8h, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	300	0	0	0	249	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	27	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	81	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160212	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	18	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	36	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	69	0	0	35	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	3	0	1	1	1	10118	0	16	0	0	40036	160000	100	40603	40600	40341	40599	40609
160204	40656	304	1	12	13	1653	1144	1	1993	248	161276	100	161083	100	161147	500	1289052	1	40503	40654	40707	20098	55	20312	161344	204	161254	202	322494	40764	40613	13	1	160201	100	99	100	100	160000	100	2	2	0	2	5665	0	1	1	1	10341	1	173	2	0	40409	160000	100	40714	40771	40659	40708	40714
160204	40608	304	1	13	13	1131	1144	0	1086	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	30	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	24	20018	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	0	0	267	0	0	30	25	160212	100	160008	100	160020	511	1280132	1	40020	40091	40090	19977	6	19990	160230	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	3	0	1	1	1	10118	0	16	0	1	40036	160000	100	40040	40103	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	300	0	0	0	0	42	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	8	16	2	1	1	6	4	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	711	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	6	16	2	1	1	6	5	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	0	744	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	20	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	2	10024	6	2	2	4	16	4	2	2	5	3	40036	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	501	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320280	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10024	6	2	2	4	16	4	2	2	4	4	40036	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	723	52	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10024	6	2	2	6	16	4	2	2	5	4	40036	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	756	52	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10024	6	2	2	4	16	4	2	2	5	3	40036	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	636	52	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10024	6	2	2	4	16	4	2	2	4	5	40036	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	501	52	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20128	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	6	16	2	1	1	4	3	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	801	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	4	16	2	1	1	6	6	40036	15	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	789	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10024	3	1	1	4	16	2	2	1	5	5	40036	15	10	160000	10	40040	40040	40040	40040	40040

UQRSHRN2 (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations