Firestorm: UQRSHRN (S) measurements

Code:

  uqrshrn h0, s0, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3084	22	1	1	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1025	1000	3037	3084	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	210	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	334	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	0	61	2547	25	1000	1000	1000	398160	1	3018	3037	3037	2414	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2629	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  uqrshrn h0, s0, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	8343	0	710	3	16	2	2	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	124	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29633	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28264	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29696	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	726	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	1	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	1335	29529	60	10028	15	10016	12	10300	71	4279864	0	30054	30131	30132	28294	12	28805	10314	22	10322	20	10326	30169	30132	3	1	10021	10	9	10	10	10000	10	0	1	3	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	0	640	2	16	2	2	29629	10000	10	30084	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	12	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  uqrshrn h0, s8, #3
  uqrshrn h1, s8, #3
  uqrshrn h2, s8, #3
  uqrshrn h3, s8, #3
  uqrshrn h4, s8, #3
  uqrshrn h5, s8, #3
  uqrshrn h6, s8, #3
  uqrshrn h7, s8, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20039	150	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	1	20029	20048	20048	9976	10	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	6	0	2	2	2	5128	3	23	1	1	20045	0	80000	100	20049	20050	20049	20049	20050
80204	20048	150	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	1	20029	20048	20048	9976	9	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	3	0	2	2	2	5128	1	23	1	1	20045	0	80000	100	20050	20049	20049	20049	20049
80204	20048	150	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	0	20029	20048	20049	9976	9	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5128	1	23	1	1	20045	0	80000	100	20049	20049	20050	20049	20049
80204	20049	150	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	1	20029	20048	20048	9976	10	9986	80128	200	80038	200	80038	20049	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5129	1	23	1	1	20045	0	80000	100	20049	20049	20049	20049	20049
80204	20049	150	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	1	20029	20048	20048	9976	9	9986	80128	200	80038	200	80038	20049	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5128	1	23	1	1	20046	0	80000	100	20049	20049	20050	20050	20049
80204	20048	150	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	0	20029	20048	20048	9976	9	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5129	1	23	1	1	20045	0	80000	100	20050	20049	20049	20049	20049
80204	20048	150	0	0	0	0	0	0	128	27	80116	100	80016	100	80028	500	640196	1	20029	20048	20048	9976	9	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	99	0	2	2	2	5128	1	23	1	1	20046	0	80000	100	20050	20050	20049	20049	20050
80204	20049	150	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	0	20029	20049	20048	9976	9	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	3	0	2	2	2	5128	1	23	1	1	20045	0	80000	100	20050	20050	20049	20049	20049
80204	20049	150	0	0	0	0	0	0	64	27	80116	100	80016	100	80028	500	640196	1	20029	20048	20048	9976	10	9986	80128	200	80038	200	80038	20049	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	12	0	2	2	2	5129	1	23	1	1	20045	0	80000	100	20049	20049	20050	20050	20049
80204	20048	150	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	0	20029	20048	20049	9976	10	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5128	1	23	1	1	20046	0	80000	100	20050	20050	20050	20049	20049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20050	150	0	515	25	80010	10	80000	10	80000	50	640000	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	3	0	5020	4	16	6	3	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	82	25	80010	10	80000	10	80000	50	640000	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	6	0	5020	4	16	4	3	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	78	0	5020	4	16	3	4	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	18	0	5020	4	16	3	4	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	1	1	4	72	0	5020	3	16	4	3	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	325	25	80010	10	80000	10	80000	50	640000	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	4	16	3	4	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	120	0	5020	4	16	4	3	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	3	16	4	3	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	3	16	4	3	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	20020	20039	20039	9996	3	10019	80010	20	80000	20	80000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	171	0	5020	4	16	4	3	20036	0	80000	10	20040	20040	20040	20040	20040

UQRSHRN (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations