Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSHL (immediate, scalar, B)

Test 1: uops

Code:

  uqshl b0, b0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371606116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100011692037203711100110001073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116221786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000373116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000373116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116221786100020382038203820382038

Test 2: Latency 1->2

Code:

  uqshl b0, b0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150091031968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382008420038
1020420037150001241968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006403162219786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000003061196862510010101001210100005028475210200182003720037184433187671001020100002010000200842003711100211091010100001024200010055076184912719966310000102022920228202762022820228
1002420272152104266044022411963112410073111001215106086528538410201982027520225184672318859106202410672201082720272202266110021109101010000104001127895074744971219955510000102013120180202752027520324
10024202741521155537440611968625100101010000101000050284752102005420037200371844331876710010201000020101692008420037111002110910101000010420010587327042427519894410000102017920180202652018220229
10024202251511103035261196532510010101000010104565028475210200902013020179184553187851001022111802211327204142046691100211091010100001002200217955074671105320000410000102036620274202732041420370
1002420264157019866044042861963118310123181010814107967628576330201982022720466184584518824107722211490221167120417204511011002110910101000010000000606506402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  uqshl b0, b8, #3
  uqshl b1, b8, #3
  uqshl b2, b8, #3
  uqshl b3, b8, #3
  uqshl b4, b8, #3
  uqshl b5, b8, #3
  uqshl b6, b8, #3
  uqshl b7, b8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815129258010810080008100800205006401322001920038200389977069989801202008003220080032200382003811802011009910010080000100000111511821612200350800001002003920039200392003920039
802042003815029258010810080008100800205006401322001920038200389977069989801202028003220080032200382003811802011009910010080000100000111511811612200350800001002003920039200392003920039
802042003815029258010810080008100800205006401322001920038200389977069989801202008003220080032200382003811802011009910010080000100000111511821612200350800001002003920039200392003920039
802042003815029258010810080008100800205006401322001920038200389977769989801202008003220080032200382003811802011009910010080000100000111511811621200350800001002003920039200392003920039
8020420038150292580108100800081008002050064013220019200382003899770699898012020080032200800322003820038118020110099100100800001000001115118216222003523800001002003920039200392003920039
8020420038150124258010810080008100800205006401322001920038200389977069989801202008003220080032200382003811802011009910010080000100000111511811612200350800001002003920039200392003920039
802042003815029258010810080008100800205006401322001920038200389977069989801202008003220080032200382003811802011009910010080000100000111511821622200350800001002003920039200392003920039
802042003815029258010810080008100800205006401322001920038200389977069989801202008003220080032200382003811802011009910010080000100100111511821621200350800001002003920039200392003920039
802042003815029258010810080008100800205006401322001920038200389977069989801202008003220080032200382003811802011009910010080000100000111511821622200350800001002003920039200392003920039
802042003815029258010810080008100800205006401322001920038200389977069989801202008003220080032200382003811802011009910010080000100000111511821612200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)d9daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500000000001022580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000000050200161600752003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000000005020081600962003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000000005020091600572003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000000005020061600882003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000000005020081600862003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000005020061600572003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000000005020081600752003580000102003920039200392003920039
8002420038150000000000602580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000000050200101600752003580000102003920039200392003920039
8002420038150000000000602580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000000050200101600952003580000102003920039200392003920039
8002420038150000000000609258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000000005020061600592003580000102003920039200392003920039