Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSHL (immediate, scalar, S)

Test 1: uops

Code:

  uqshl s0, s0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150006116862510001000100026452102018203720371571318951000100010002037203711100110000073216111786100020382038203820382038
10042037150006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037151006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100011073116111786100020382038203820382038
10042037150006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100002473116111786100020382038203820382038
10042037150006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150006116862510001000100026452102018203720371571318951000100010002037203711100110001073116111786100020382038203820382038
100420371500126116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150006116862510001000100026452102018203720371571318951000100010002037203711100110000673116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  uqshl s0, s0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000000001031968625101001001000010010000500284878520018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820181200852003820086
102042003715000010005621968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611198590100001002003820038200382013320038
10204200371500000000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371490000000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200371500000000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000003071011611197910100001002003820038200862003820038
10204200371500000000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150008219686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150008219686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037149006119686251001010100001010152502847521020018200372003718443318767100102010000201000020037200371110021109101010000103640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  uqshl s0, s8, #3
  uqshl s1, s8, #3
  uqshl s2, s8, #3
  uqshl s3, s8, #3
  uqshl s4, s8, #3
  uqshl s5, s8, #3
  uqshl s6, s8, #3
  uqshl s7, s8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2map dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200501500232258010810080008100800205006401321520019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185116020035800001002003920039200392003920039
8020420038150029258010810080008100800205006401321520019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185116020035800001002003920039200392003920039
8020420038150029258010810080008100800205006401321520019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185116020035800001002003920039200392003920039
8020420038150029258010810080008100800205006401321520019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185116020035800001002003920039200392003920039
80204200381500138258010810080008100800205006401321520019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185116020035800001002003920039200392003920039
80204200381500138258010810080008100800205006401321520019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185116020035800001002003920039200392003920039
80204200381500389258010810080008100800205006401321520019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185116020035800001002003920039200392003920039
8020420038150029258010810080008100800205006401321520019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185116020035800001002003920039200392003920039
8020420038150029258010810080008100800205006401321520019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185116020035800001002003920039200392003920039
8020420038150029258010810080008100800205006401321520019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185116020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150000000003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000000000050202160322003508780000102003920039200392003920039
8002420038150000000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000000000050202160232003507380000102003920039200392003920039
8002420038150000000006025800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000000000050203160232003508880000102003920039200392003920039
8002420038150000000303925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000000000050202160222003507380000102003920039200392003920039
8002420038150000000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000000000050202160222003508880000102003920039200392003920039
8002420038150000000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000000030050203160322003508880000102003920039200392003920039
8002420038150000000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000001000050202160222003507380000102003920039200392003920039
8002420038150000000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000000000050202160222003507380000102003920039200392003920039
8002420038150000000006025800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000000030050203160322003507380000102003920039200392003920039
8002420038150000000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000000000050203162222003507380000102019020039200392003920039