Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSHL (immediate, vector, 2S)

Test 1: uops

Code:

  uqshl v0.2s, v0.2s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715000000611686251000100010002645210201820372037157131895100010001000203720371110011000000073116111786100020382038203820382038
1004203715000000611686251000100010002645210201820372037157131895100010001000203720371110011000000073116111786100020382038203820382038
1004203715000000941686251000100010002645210201820372037157131895115210001000203720371110011000000073116111786100020382038203820382038
1004203715000000611686251000100010002645210201820372037157131895100010001000203720371110011000000073116111786100020382038203820382038
1004203716000000611686251000100010002645210201820372037157131895100010001000203720371110011000000073116111786100020382038203820382038
1004203715000000611686251000100010002645210201820372037157131895100010001000203720371110011000000073116111786100020382038203820382038
1004203715000000611686251000100010002645211201820372037157131895100010001000203720371110011000001073116111786100020382038203820382038
1004203715000000821686251000100010002645211201820372037157431895100010001000203720371110011000000073116111786100020382038203820382038
1004203715000000611686251000100010002645210201820372037157131895100010001000203720371110011000000073116111786100020382038203820382038
1004203715000000611686251000100010002645210201820372037157131895100010001000203720371110011000000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  uqshl v0.2s, v0.2s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000018006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715100000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000024006119686251010010010000100100005002847521020018200372003718424318760102722041016520210166201222008621102011009910010010000100000102208571011611197910100001002003820038200382003820038
1020420085150000015610406119686251010010010000100100005002847521020018200372003718421718763101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
10204200841510000000611967525101001001000010010000653285257702016220262202751843225187451074121410660220108292022820229611020110099100100100001000030128003735156221996928100001002027820280202762022920278
1020420277152015066335202548196301261017712510060134107606562852577120162202722027618429231883810742218103942121083220276202666110201100991001001000010040201010048827157211997021100001002027620279202792027820277
1020420273151105454044012127196201041019213010012139107606852853761120198203112027818425291883610898220104992141083220275202786110201100991001001000010004210211948847264122000328100001002032720087202752032520374
1020420322151110000012019686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000371011611197910100001002003820038200382003820038
102042003715000000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150012611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
1002420037150030611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500342611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216231978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
1002420037150018941968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
1002420037150027611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010100640216221978610000102003820038200382003820038
10024200371500366611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
1002420037150090611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  uqshl v0.2s, v8.2s, #3
  uqshl v1.2s, v8.2s, #3
  uqshl v2.2s, v8.2s, #3
  uqshl v3.2s, v8.2s, #3
  uqshl v4.2s, v8.2s, #3
  uqshl v5.2s, v8.2s, #3
  uqshl v6.2s, v8.2s, #3
  uqshl v7.2s, v8.2s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acafc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591500000000000296280108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381500000000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
802042003815000000001200292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381500000000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
802042003815000000002100292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111518501600200350800001002003920039200392003920039
80204200381500000000300292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381500000000900292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381500000000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381500000000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000010000111511801600200350800001002003920039200392003920039
80204200381490000000900292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000007111511801600200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500000120392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200216322003580000102003920039200392003920039
800242003815000001980392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200316322003580000102003920039200392003920039
80024200381500000120392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200216232003580000102003920039200392003920039
8002420038150000000612580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200416222003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200216222003580000102003920039200392003920039
80024200381500000240392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200216222003580000102003920039200392003920039
800242003815000003810392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200216232003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200316222003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050200216222003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200316222003580000102003920039200392008820039