Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSHL (immediate, vector, 4H)

Test 1: uops

Code:

  uqshl v0.4h, v0.4h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150276116862510001000100026452112018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073216221787100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715096116862510001000100026452112018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073216221816100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073216221786100020382038203820382038

Test 2: Latency 1->2

Code:

  uqshl v0.4h, v0.4h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000020819686251010010010000100100005002847521120018200372003718428718741101002001000820010008200372003711102011009910010010000100000000011171701600198010100001002003820038200382003820038
1020420037150000306119686251010010010000100100005002847521120018200372003718428718741101002001000820010008200372003711102011009910010010000100000000011171801600198000100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038
10204200371500006606119686251010010010000100100005002848785120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038
10204200371500007506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000003000071011611197910100001002003820038200382003820038
102042003715000000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000000108000071011611197910100001002003820038200382003820038
10204200371500000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000087000071011611197910100001002003820038200382003820038
10204200371500000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000090000071011611197910100001002003820038200382003820038
1020420037150000306119686251010010010000100100005802848785120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500251196862510010101000010100005028475210200182003720037184433187671001020100002010180200372003711100211091010100001000640316221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010015640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  uqshl v0.4h, v8.4h, #3
  uqshl v1.4h, v8.4h, #3
  uqshl v2.4h, v8.4h, #3
  uqshl v3.4h, v8.4h, #3
  uqshl v4.4h, v8.4h, #3
  uqshl v5.4h, v8.4h, #3
  uqshl v6.4h, v8.4h, #3
  uqshl v7.4h, v8.4h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)fetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059151050425801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000132111511816020035800001002003920039200392003920039
8020420038150029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100553111511816020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115111511816020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
8020420038150029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100300111511816020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
8020420038150029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100045111511816020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150000000000392580010108000010800005064000015200192003820038999631001880010208000020800002003820038118002110910108000010000006000050205516552003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400001020019200382003899963100188001020800002080000200382003811800211091010800001000000300050205816752003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400001520019200382003899963100188001020800002080000200382003811800211091010800001000000000050205716582003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400001520019200382003899963100188001020800002080000200382003811800211091010800001000000600150205716662003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400001520019200382003899963100188001020800002080000200382003811800211091010800001000000000050205716752003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400001520019200382003899963100188001020800002080000200382003811800211091010800001000000000050205616672003580000102003920039200392003920039
8002420038150000000450039258001010800001080000506400001520019200382003899963100188001020800002080000200382003811800211091010800001000000300050205516742003580000102003920039200392003920039
800242003815000000018004192580010108000010800005064000015200192003820038999631001880010208000020800002003820038118002110910108000010000007500050205816652003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400001020019200382003899963100188001020800002080000200382003811800211091010800001000000000050205816562003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400001520019200382003899963100188001020800002080000200382003811800211091010800001000050900050205616662003580000102003920039200392003920039