Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSHL (immediate, vector, 8H)

Test 1: uops

Code:

  uqshl v0.8h, v0.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116221786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371508716862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000373116111786100020382038203820382038
100420371606116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  uqshl v0.8h, v0.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715000073619686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521020018200372003718421318745101002041000020010000200372003711102011009910010010000100027102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500005361968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010160640216221978610000102003820038200382003820038
10024200371500006119686251001010100001010000502847521120018200372008418443318767100102010000201000020037200371110021109101010000103501640216221978610000102003820038200382003820038
1002420037150000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100990640216221978610000102003820038200382003820038
1002420037150000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001001350640216221978610000102003820038200382003820038
10024200371500006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100210640216221978610000102003820038200382003820038
1002420037150000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010030640216221978610000102003820038200382003820038
1002420037150000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  uqshl v0.8h, v8.8h, #3
  uqshl v1.8h, v8.8h, #3
  uqshl v2.8h, v8.8h, #3
  uqshl v3.8h, v8.8h, #3
  uqshl v4.8h, v8.8h, #3
  uqshl v5.8h, v8.8h, #3
  uqshl v6.8h, v8.8h, #3
  uqshl v7.8h, v8.8h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200471500000000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180160020035800001002003920039200392003920039
80204200381500000000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180160020035800001002003920039200392003920039
80204200381500000000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180160020035800001002003920039200392003920039
80204200381500000000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180160020035800001002003920039200392003920039
80204200381500000000094258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180160020035800001002003920039200392003920039
80204200381500000000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180160020035800001002003920039200392003920039
80204200381500000000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180160020035800001002003920039200392003920039
80204200381500000000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180160020035800001002003920039200392003920039
80204200381500000000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180160020035800001002003920039200392003920039
80204200381500000000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180620020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd0d5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115000000000001072580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020031604220035080000102003920039200392003920039
80024200381500000000000822580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020041602420035080000102003920039200392003920039
80024200381500000000000822580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020021602320035080000102003920039200392003920039
80024200381500000000000882580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020021602420035080000102003920039200392003920039
80024200381500000000000962580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020041604220035080000102003920039200392003920039
800242003815000000000002182580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020041604420035080000102003920039200392003920039
800242003815000000000002182580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020041602420035080000102003920039200392003920039
800242003815000000000009672580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020041602420035080000102003920039200392003920039
80024200381500000000000902580010108000010800005064000012001920038200389996031001880010208000020800002003820038118002110910108000010000000005020021602420035080000102003920039200392003920039
80024200381500000000000822580010108000010800005064000012001920038200389996031001880010208000020800002003820038218002110910108000010000003005020041604220035080000102003920039200392003920039