Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSHRN2 (8H)

Test 1: uops

Code:

  uqshrn2 v0.16b, v1.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230001072548251000100010003983131301830373037241532895100010002000303730371110011000473116112630100030383038303830383038
10043037220002592548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230002562548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037220002222548251000100010003983130301830373037241532895100010002000303730372110011000173116112630100030383038303830383038
10043037220001952539251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230001702548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037220002542548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
1004303723000612548251000100010003983131301830373037241532895100010002000303730371110011000173116112630100030383038303830383038
10043037220003092548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037220004412548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  uqshrn2 v0.16b, v1.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000300061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000071021611296340100001003003830038300383003830038
1020430037224000024264061295482510100100100001001000050042788153001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500003150061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500004650061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500003720061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500003630061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037225000030264061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722500004290061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003008530037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250000270061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250000210061295482510100100100001001000050042773133001830037300372826503287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722400000000061295482510010101000010100006042773131300183003730037282873287671001020100002020000300373003711100211091010100001000001007052162229630010000103003830038300383003830038
100243003722400000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722400000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000000726295482510010121000012100005042773130300183003730037282873287671016320100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430131224000000000536295482510010101000010100005042773130300183003730037282873287671001220100002020000300373003711100211091010100001000000006402166229632210000103003830038300383003830038
100243003722500000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000000061295482510010101002410100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000000061295482510012101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000000103295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001002000006402162229630210000103003830038300383003830038

Test 3: Latency 1->2

Code:

  uqshrn2 v0.16b, v0.8h, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225030029329547251010010010000100100005004277160130018030037300372825262874010100200100082002001630037300371110201100991001001000010001001117181629646100001003003830038300383003830038
1020430037224018072629547251010010010000100100005004277160030018030037300372827162874110100200100082002001630037300371110201100991001001000010001001117171629646100001003003830038300383003830038
102043003722503006129547251010010010000100100005004278507130018030037300372827162874010100200100082002001630037300371110201100991001001000010000031117181629645100001003003830038300383003830038
102043003722501806129547251010010010000100100005004277160130018030037300372827172874010100200100082002001630084300852110201100991001001000010000001117181629645100001003018130038300383003830038
102043003722506906129547251010010010000100100005004277160130018030037300372827162874110100200100082002001630037300371110201100991001001000010000001117181629646100001003003830038300383003830038
102043003722402706129547251010010010000100100005004277160130018030037300372827172874010100200100082002001630037300371110201100991001001000010000001117181629645100001003003830038300383003830038
10204300372250906129547251010010010000100100005004277160130018030037300372827172874110100200100082002001630037300371110201100991001001000010000001117181629646100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160130018030037300372827162874010100200100082002001630037300371110201100991001001000010000001117181629645100001003003830038300383003830038
102043003722501206129547251010010010000100100005004277160130018030037300372827162874110100200100082002001630037300371110201100991001001000010000001117181629645100001003003830038300383003830038
102043003722501506129547251010010010000100100005004277160130018030037300372827172874010100200100082002001630037300371110201100991001001000010000001117181629646100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372259006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100640416342962910000103003830038300383003830038
10024300372251506129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100640316442962910000103003830038300383003830038
1002430037225906129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100640416442962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100640416442962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100640416432962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100640316342962910000103003830038300383003830038
10024300372251506129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100640416432962910000103003830038300383003830038
10024300372255406129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100640416432962910000103003830038300383003830038
1002430037224006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100640416432962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100640416432962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uqshrn2 v0.16b, v8.8h, #3
  movi v1.16b, 0
  uqshrn2 v1.16b, v8.8h, #3
  movi v2.16b, 0
  uqshrn2 v2.16b, v8.8h, #3
  movi v3.16b, 0
  uqshrn2 v3.16b, v8.8h, #3
  movi v4.16b, 0
  uqshrn2 v4.16b, v8.8h, #3
  movi v5.16b, 0
  uqshrn2 v5.16b, v8.8h, #3
  movi v6.16b, 0
  uqshrn2 v6.16b, v8.8h, #3
  movi v7.16b, 0
  uqshrn2 v7.16b, v8.8h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008815100129292580116100800161008002850064019612004520065200656128012820080028200160268200652006521160201100991001001600001000011110119016002006211600001002006620066200662006620066
16020420065150000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000011110119016002006201600001002006620066200662006620066
16020420065151000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000011110119016002006201600001002006620066200662006620066
16020420065150000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000011110119016002006201600001002006620066200662006620066
16020420065150000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000011110119016002006201600001002006620066200662006620066
1602042006515100237292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001002011110119016002006201600001002006620066200662006620066
16020420065150000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000011110119016002006201600001002006620066200662006620066
160204200651500018292580116106800161008002850064019612004520065200656128012820080028200160056201312006511160201100991001001600001000011110119016002006201600001002006620066200662006620066
160204200651500015292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000011110119016002006201600001002006620066200662006620066
16020420065151000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000011110119016002006201600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242007715000004201572980010108000010800005064000000020041200712006032280010208000020160000200602006011160021109101016000010000100356222034322141820050201160000102005220054200542005220052
160024200511500000600452980010108000010800005064000001520043200602006032280010208000020160000200512005111160021109101016000010000100413512027111191820050201160000102005420052200522005220052
1600242005115000004500452780010108000010800005064000011520032200512005132280010208000020160000200532005311160021109101016000010000100408511825211171220048211160000102005220052200522005220054
160024200531510000900452780010108000010800005064000011520034200622005332280010208000020160000200512005111160021109101016000010000100388511325111161720048201160000102005220052200522005220054
1600242005315000002400452780010108000010800005064000010520032200602005132280010208000020160000200512005111160021109101016000010000100393111725111181920050201160000102005220052200542005420052
160024200531500000000452780010108000010800005064000010020034200512005132280010208000020160000200512005311160021109101016000010000100383111527211131620048201160000102005220052200522005220054
16002420051150000072004527800101080000108000050640000110200322005120051322800102080000201600002005120051111600211091010160000100069100368511025111162120048201160000102005220052200522005420052
1600242005115000001500682780010108000010800005064000010520032200622005132280010208000020160000200532005311160021109101016000010000100393111727211151720048211160000102005220054200542005220052
1600242005115000005100452780010118000010800005064000010520032200512005132280010208000020160000200532005311160021109101016000010000100413111225111171620050201160000102005220052200522005220052
160024200511500000000452780010108000010800005064000010520134200532005132280010208000020160000200512005111160021109101016000010000100348511727111151720048201160000102005220052200522005220052

Test 5: throughput

Count: 16

Code:

  uqshrn2 v0.16b, v16.8h, #3
  uqshrn2 v1.16b, v16.8h, #3
  uqshrn2 v2.16b, v16.8h, #3
  uqshrn2 v3.16b, v16.8h, #3
  uqshrn2 v4.16b, v16.8h, #3
  uqshrn2 v5.16b, v16.8h, #3
  uqshrn2 v6.16b, v16.8h, #3
  uqshrn2 v7.16b, v16.8h, #3
  uqshrn2 v8.16b, v16.8h, #3
  uqshrn2 v9.16b, v16.8h, #3
  uqshrn2 v10.16b, v16.8h, #3
  uqshrn2 v11.16b, v16.8h, #3
  uqshrn2 v12.16b, v16.8h, #3
  uqshrn2 v13.16b, v16.8h, #3
  uqshrn2 v14.16b, v16.8h, #3
  uqshrn2 v15.16b, v16.8h, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440059300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000001111011801600400361600001004004040040400404004040040
16020440039299030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000003001111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000001111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000031111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000001111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000001111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394010219977619990160120200160032202320064400394020311160201100991001001600001000001031111011803900400361600001004004040040400404004040040
160204400392994830251601081001600081001600205001280132040020400394003919977620024160120200160032200320064400394003911160201100991001001600001000000001111011801600400361600001004004040040400404004040040
16020440039299030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000001111011801600400361600001004004040040400404004040040
16020440039299030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000001111011801600400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244003930004625160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000100228212816221241740036305160000104004040040400404004040040
160024400393000466016010810160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010001002213712316211242440036155160000104004040040400404004040040
1600244003930002162516001010160000101600005012800001110400204003940039199963200191601222016000020320000400394003911160021109101016000010001002213712516211242540036155160000104004040040400404004040040
160024400393000462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010001002213712616211232340036155160000104004040040400404004040040
160024400393000462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010001002213712416211242540036155160000104004040040400404004040040
160024400393000462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010001002213712516211232340036155160000104004040040400404004040040
160024400393000462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010101002213712516211242540036155160000104004040040400404004040040
160024400392990462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010001002213712416211242440036155160000104004040040400404004040040
160024400393000462516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010101002213712316211232340036155160000104004040040400404004040145
160024400393000522516001010160000101600005012800001110400204003940039199963200191600102016000020320000400394003911160021109101016000010001002213712216211232340036155160000104004040040400404004040040