Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSHRN (H)

Test 1: uops

Code:

  uqshrn b0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722061254725100010001000398160130183037303724143289510001000100030373037111001100001273116112629100030383038303830383038
100430372206125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100001273116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001005100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372206125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372206125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  uqshrn b0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4e5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500005362954702510100100100001001000050042771603001830037300372826432874510100200100002001000030037300371110201100991001001000010021871471011611296330100001003003830038300383003830038
102043003722500006312954702510100100100001001000050042771603001830037300372826432874510100200100002001000030037300371110201100991001001000010029371011611296330100001003003830038300383003830038
10204300372250000726295470251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001007371011611296330100001003003830038300383003830038
102043003722500007262954702510100100100001001000050042771603001830037300372826432874510100200100002001000030037300371110201100991001001000010026371011611296330100001003003830038300383003830038
102043003722500006129547025101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100010571011611296330100001003003830038300383003830038
1020430037225000216129547025101001001000010010000500427716030018300373003728264328745101002001000020010000300373003711102011009910010010000100261125371011611296330100001003003830038300383003830038
10204300372240000612954702510100100100001001000050042771603001830037300372826432874510100200100002001000030037300371110201100991001001000010031371011611296330100001003003830038300383003830038
10204300372250000612954702510100100100001001000050042771603001830037300372826432874510100200100002001000030037300371110201100991001001000010026371011611296330100001003003830038300383003830038
10204300372250000612954702510100100100001001000050042771603001830037300372826432874510100200100002001000030037300371110201100991001001000010027371011611296330100001003003830038300383003830038
10204300372250000612954702510100100100001001000050042771603001830037300372826432874510100200100002001000030037300371110201100991001001000010043371011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000000612954725100101010000101000050427716003001830037300372828603287671001020100002010000300373003711100211091010100001000010006402162229629010000103003830038300383003830038
10024300372250000000612954725100101010000101000050427716003001830037300372828603287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
10024300372250000000612954725100101010000101000050427716013001830037300372828603287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
10024300372250000000612954725100101010000101000050427716003001830037300372828603287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
10024300372250000000612954725100101010000101000050427716003001830037300372828603287671001020100002010000300373003711100211091010100001000000006402162229629010000103008630038300383003830038
10024300372250000000612954725100101010000101000050427716003001830037300372828603287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160030018300373003728286732876710010201000020100003003730037111002110910101000010000003306402162229629010000103003830038300383003830038
10024300372250000000612954725100101010000101000050427716003001830037300372828603287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000001242954725100101010000101000050427716003001830037300372828603287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
10024300372250000000612954725100101010000101000050427716003001830037300372828603287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  uqshrn b0, h8, #3
  uqshrn b1, h8, #3
  uqshrn b2, h8, #3
  uqshrn b3, h8, #3
  uqshrn b4, h8, #3
  uqshrn b5, h8, #3
  uqshrn b6, h8, #3
  uqshrn b7, h8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915000000050525801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000053090111511811600200360800001002004020040200402004020040
80204200391500000003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000900111511801600200360800001002004020040200402004020040
80204200391500000004025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000010120111511801600200360800001002004020040200402004020040
8020420039150001030302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000004501740111511801600200360800001002004020040200402004020040
8020420039150000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000000111511801600200360800001002004020040200402004020040
8020420039150000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000030111511801600200360800001002004020040200402004020040
8020420039150000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000000111511801600200360800001002004020040200402004020040
8020420039150000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000005204780111511801600200360800001002004020040200402004020040
8020420039150000000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000001000111511801600200360800001002004020040200402004020040
80204200391500000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000047000111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010020050202161120036080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010010650201161120036080000102011420040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010010050201161120036080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000050201161120036080000102004020040200402004020040
80024200391500040258001010800001080000506400001200692003920039999631001980010208000020800002003920039118002110910108000010000050201161120036080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020800002003920089118002110910108000010000050201161120036080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010090188350201161120036080000102004020040200402004020040
800242003915000705258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000050201161120036080000102004020040200402004020040
80024200391500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000050201161120036080000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100250050201161120036080000102004020040200402004020040