Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSUB (scalar, H)

Test 1: uops

Code:

  uqsub h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073216112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100001873116112630100030383038303830383038
100430372266125482510001000100039831330183037303724153289510001000200030373037111001100002473116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100002473116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqsub h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510125125100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000710116112963425100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071001611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011711296340100001003003830038300383003830038
1020430037225061295482510125125100001251000050042773131300183003730037282653287451010020010000202200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037225061295482510125100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000010071021611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287441010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037224061295482510100100100001001000050042773131300183003730037282653287441010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
1020430037225961295482510100100100001001000050042773130300183003730037282653287451010020210000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500001470061295482510028101001610100006642773130300543003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300853008530038
1002430037225003000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000020006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000606402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229702010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000103295482510010101000010100005042773130300183003730037282873287671001020101612020000300373013211100211091010100001000000306632162329630010000103013230133300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqsub h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303005430037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000006071011611296340100001003003830038300383003830038
102043003722400892954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
1020430037225005362954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000000210295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000431295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000340295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000107295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000191295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000103295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000170295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000010006402162229630010000103003830038300383003830038
10024300372250000000170295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000258295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000210295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uqsub h0, h8, h9
  uqsub h1, h8, h9
  uqsub h2, h8, h9
  uqsub h3, h8, h9
  uqsub h4, h8, h9
  uqsub h5, h8, h9
  uqsub h6, h8, h9
  uqsub h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150412580100100800001008000050064000000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000051100021611200360800001002004020040200402004020040
8020420039150412580100100800001008000050064000000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000051100011611200360800001002004020040200402004020040
8020420039150412580100100800001008000050064000000200200200482003999730399978010020080000200160000200392003911802011009910010080000100000051100011611200360800001002004020040200402004020040
80204200391504292580100100800001008000050064000010200200200392003999730399978010020080000200160000200392003911802011009910010080000100000051100011611200360800001002004020040200402004020040
8020420039150412580100100800001008000050064000000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000051100011611200360800001002004020040200402004020040
80204200391501502580100100800001008000050064000000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000051100011611200360800001002004020040200402004020040
80204200391501692580100100800001008000050064000000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000051100011611200360800001002004020040200402004020040
8020420039150412580100100800001008000050064000000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000051100011611200360800001002004020040200402004020040
8020420039150412580100100800001008000050064000000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000051100011611200360800001002004020040200402004020040
8020420039150412580100100800001008000050064000000200200200392003999730399978010020080000200160000200392003911802011009910010080000100000051100011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150100004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050201316342003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050200316442003680000102004020040200402004020040
8002420104150000004025800101080000108010450640000020020200392003999963100198001020800002016000020039200391180021109101080000100050203416322003680000102004020040200402004020040
8002420145150010004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050200416632003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050200316552003680000102004020040200402004020040
80024200391500000010325800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050200416442003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050200316352003680000102004020040200402004020040
8002420039150000006325800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050200416442003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000103050200516532003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100350200316442003680000102004020040200402004020040