Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSUB (vector, 4H)

Test 1: uops

Code:

  uqsub v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230126254825100010001000398313130183037303724153289510001000200030373037111001100010073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000373116112630100030383038303830383038
1004303722061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037220612548251000100010003983131301830373037241520289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724156289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723661254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqsub v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071021611296340100001003003830038300383003830038
102043003722400006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225000025329548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500006129548251012610010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722400000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006403162229630010000103003830038300383003830038
100243003722500000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000002706402162229630010000103003830038300383003830038
100243003722500000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722400000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722400000000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
100243003722500000030061295484410010101000010101495042773131300183008530037282873287671016120101682020000300843003721100211091010100001000000306402162729630010000103003830038300853003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000102406402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqsub v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225002712295482510100100100001001000050042773131300180300373003728265328745101002021000020020000300373003711102011009910010010000100000007103162229634100001003003830038300383003830038
10204300372250082295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000830007102162229634100001003003830038300383003830038
102043003722500191295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
102043003722512061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
102043003722500348295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
102043003722400212295482510100100100001001000050042773131300180300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372256129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372256129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372256129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10025300372256129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372256129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372256129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372336129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372256129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
10024300372256129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100640216222963010000103003830038300383003830038
100243003722461295482510010101000013100005042773130300183003730037282873287671001020100002020000300373003721100211091010100001015640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uqsub v0.4h, v8.4h, v9.4h
  uqsub v1.4h, v8.4h, v9.4h
  uqsub v2.4h, v8.4h, v9.4h
  uqsub v3.4h, v8.4h, v9.4h
  uqsub v4.4h, v8.4h, v9.4h
  uqsub v5.4h, v8.4h, v9.4h
  uqsub v6.4h, v8.4h, v9.4h
  uqsub v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150000000000423258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511031611200360800001002004020040200402004020040
802042003915000000000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020090200402004020040
802042003915000000000041258020510080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402010020040
8020420039150000000000238258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000000000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000000000062258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000000000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000000000057258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000000000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011621200360800001002004020040200402004020040
802042003915000000000041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500000325258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020116112003680000102004020040200402004020040
8002420039150000040258030110800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000005020116112003680000102004020040200402004020040
8002420039150000061258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020116112003680000102004020040200402004020040
8002420039150000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020116112003680000102004020040200402004020040
80024200391500000124258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001005005020116112003680000102004020040200402004020040
8002420039150000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001001005020116112003680000102004020040200402004020040
8002420039150000040448001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020116112003680000102004020040200402004020040
80024200391500000988258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020116112003680000102004020040200402004020040
8002420039150000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020116112003680000102004020040200402004020040
8002420039150000084258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020116112003680000102004020040200402004020040