Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSUB (vector, 4S)

Test 1: uops

Code:

  uqsub v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230886125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722123061254825100010001000398313130183037303724153289510001000200030373037111001100015373116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110002073116112630100030383038303830383038
10043037231206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230010325482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqsub v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010010007102161129634100001003003830038300383003830038
1020430037225601242954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010030007101161129634100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722508202954825101001001000010010000500427731303001830085300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000107101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010010007101161129634100001003003830038300383003830228
102043003722507262954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000020006403162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000030306402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313030018030037300372828732876710010201000020200003003730037111002110910101000010000430906402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000010006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqsub v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250006129548251010010010000100100005004277313030018030037300372826532874510100200100002002000030037300371110201100991001001000010000710021622296340100001003003830228300383003830038
10204300372250016129548251010010010000100100005004277313030018030037300372826532874510100200100002002000030037300371110201100991001001000010000710021622296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018030037300372826532874510100200100002002000030037300371110201100991001001000010000710021622296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018030037300372826532874510100200100002002000030037300371110201100991001001000010000710021622296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018030037300372826532874510100200100002002000030037300371110201100991001001000010000710021622296340100001003003830038300383003830038
102043003722400061295482510100100100001001000050042773130300180300373003728265328745101002001000020020000300373003711102011009910010010000100007100216222963424100001003003830038301833003830038
10204300372250006129548251010010010000100100005004278561030018030037300372826532874510100200100002002000030037300371110201100991001001000010000710021622296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018030037300372826532874510100200100002002000030037300371110201100991001001000010000710021622296340100001003003830038300383003830038
10204300372240006129548251010010010000100100005004277313030018030037300372826532874510100200100002002000030037300371110201100991001001000010000710021622296340100001003003830038300383003830038
10204300372240006129548251010010010000100100005004277313030018030037300372826532874510100200100002002000030037300371110201100991001001000010000710021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722507262954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722506312954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671016020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038302283003830038
1002430037224026232954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
100243003722504412954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000003640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038301803003830038

Test 4: throughput

Count: 8

Code:

  uqsub v0.4s, v8.4s, v9.4s
  uqsub v1.4s, v8.4s, v9.4s
  uqsub v2.4s, v8.4s, v9.4s
  uqsub v3.4s, v8.4s, v9.4s
  uqsub v4.4s, v8.4s, v9.4s
  uqsub v5.4s, v8.4s, v9.4s
  uqsub v6.4s, v8.4s, v9.4s
  uqsub v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015008562580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000063051106161120036800001002004020040200402004020040
802042003915001532580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000190051101161120036800001002004020090200402004020040
80204200391500412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915005632580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
80204200391500412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150077125801001008000010080000500640000200202003920039997339997801002008000020016028420039200391180201100991001008000010000263051101161120036800001002004020040200402004020040
80204200391490412580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150010652580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
802042003915009262580100100800001008000050064000020020200392003999733999780100200800002001600002003920039118020110099100100800001000010051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010100502061652200362080000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010100502041642200361580000102004020143200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080099201602082003920039118002110910108000010000502051644200361580000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000502021624200361580000102004020040200402004020040
80024200391500082258001010802951080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000050202164520036080000102004020197200402004020040
80024200391500940548001010801941080000506400001200202003920039999631001980010208010620160208200392019311800211091010800001010578502041624200361580000102004020040200402004020040
800242003915009811258001010800001080000506400001203052034820402100601110019800102080000201600002003920039118002110910108000010000502021642200361980000102004020040200402004020040
80024200391500271032580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000502041642200362180000102004020040200402004020040
8002420039150012402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000502041624200361580000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000502021644200361580000102004020040200402004020040