Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSUB (vector, 8B)

Test 1: uops

Code:

  uqsub v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722132886125482510001000100039831313018303730372415328951000100020003037303711100110000373216222630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000200030373037111001100001273216222630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
10043037220025125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
10043037220061254825100010001000398313030183037303724153289510001000200030373037111001100003973216222630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqsub v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007100116112963414100001003003830038300383003830038
102043003722500072629548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
102043003722500095329548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225000131029548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
102043008422500091529548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225006094129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
1020430037225000146829548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830085300383003830038
102043003722500094629548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710011611296340100001003003830086300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722505362954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001006403162229630010000103003830038300383003830038
100243003722505362954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722512612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001006402162229630110000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383008530038
10024300372250612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722504412954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqsub v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731303001830037300372827262874110100200100082002001630037300371110201100991001001000010001117170160029647100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372827272874010100200100082082001630037300371110201100991001001000010001117180160029647100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722506172954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161029634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000266295482510010101000010100005042773131300183003730037282873287671001020100002020000300373022611100211091010100001000000006441516111029630010000103003830038300383003830038
1002430037225000000266295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000306446168829630010000103003830038300383003830038
100243003722500000026629548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000644516101029630010000103003830038300383003830038
100243003722500000026629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000000644524101029630010000103003830038300383008630038
10024300372250000132021082954825100101010000101000050427731313001830084300372828732876710010201065920219603027130322511002110910101000010242121676327111156171229848010000103008530038300383003830038
10024300372250030017626177295482510010101000014100005042773130300183003730085282873287671001020100002020000300373003711100211091010100001000000006861349121129810210000103018030275302253050430324
100243027522610445376162117029539641001010100001010000504280027130054300373003728293328767100102010324202000030037300841110021109101010000100000000644623101029708010000103003830038300383003830038
100243003722500000026229548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000000644516101029630010000103003830038300383003830038
1002430037226000000262295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006441016101029630010000103003830038300383003830038
10024300372250000002104295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000006441116101029630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uqsub v0.8b, v8.8b, v9.8b
  uqsub v1.8b, v8.8b, v9.8b
  uqsub v2.8b, v8.8b, v9.8b
  uqsub v3.8b, v8.8b, v9.8b
  uqsub v4.8b, v8.8b, v9.8b
  uqsub v5.8b, v8.8b, v9.8b
  uqsub v6.8b, v8.8b, v9.8b
  uqsub v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200481500000363041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511021611200360800001002004020040200402004020040
802042003915000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915001000083258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000001778862258010010980099100800005866408201200202003920039997339997801002008000020016000020039200391180201100991001008000010000100511011611200360800001002004020040200402004020040
802042003915000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000003511011611200360800001002004020040200402004020040
802042003915000000041258010010080000100800005006400001200712003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040
802042003915000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000003511011611200360800001002004020040200402004020040
802042003915000000041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000000511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9cfd0d5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420040150327402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502004160422003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502004160242003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502003160442008780000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502004160422003680000102004020040200402004020040
800242003915072402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000502004160242003680000102004020040200402004020040
8002420039150441402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000502004160422003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020160000200392003921800211091010800001000502002160242003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980116208000020160000200392003911800211091010800001000502004160352003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502004160442003680000102004020040200402004020040
800242003915001352580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000502004160342003680000102004020040200402004020040