Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSUB (vector, 8H)

Test 1: uops

Code:

  uqsub v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254844100010001000398313130183037303724153289510001000200030373037111001100010373116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037220105254825100010001000398313130183037303724153289510001000200030373037111001100010073116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  uqsub v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000058000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
102043003722500106295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830084300383003830038
10204300372320061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224000000001052954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006404162229630010000103003830038300383003830038
100243003722500000000842954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162329630010000103003830038300383003830038
100243003722500000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830085300383003830038
100243003722500000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162329630010000103003830038300383003830038
10024300372250000000020282954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162329630010000103003830038300383003830038
100243003722500000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
1002430037225000000002512954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037211002110910101000010000000006402162329630010000103003830038300383003830038
100243003722500000000822954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  uqsub v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224000612954825101001001000010010000500427731330018030037300372827276287411010020010008200200163003730037111020110099100100100001000011171801600296460100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018030037300372827206287411010020010008200200163003730037111020110099100100100001000011171801600296470100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018030037300372827206287401010020010008200200163003730037111020110099100100100001000011171801600296460100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018030037300372827206287411010020010008200200163003730037111020110099100100100001001311171701600296460100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372252112612954825101001001000010010149500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250012612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372250031032954825101001001000010010000500427731330018030037300372826503287451010020010000204200003003730037111020110099100100100001000300071011611296340100001003003830038300383003830038
10204300372250012612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296560100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018030037300372826503287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722400126129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000101012640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250001032954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830085
1002430037226000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250027612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010103640216222963010000103003830038300383003830038
10024300372251201242954825100101010000101000050427731303001830037300372828732876710010201017220200003003730037111002110910101000010223640216222963010000103003830038300383003830038
100243003722500276612954825100101010000101000050427731303001830037300372828732876710459201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225000612954825100101510000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  uqsub v0.8h, v8.8h, v9.8h
  uqsub v1.8h, v8.8h, v9.8h
  uqsub v2.8h, v8.8h, v9.8h
  uqsub v3.8h, v8.8h, v9.8h
  uqsub v4.8h, v8.8h, v9.8h
  uqsub v5.8h, v8.8h, v9.8h
  uqsub v6.8h, v8.8h, v9.8h
  uqsub v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039150083258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102161120036800001002004020040200402004020040
80204200391500182258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200202003920090999039997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161220036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150083258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150341258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000050203163220036080000102004020040200402004020040
80024200391500013525800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000050203162320036080000102004020040200402004020040
80024200391500017025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000050203163320036080000102004020040200402004020040
80024200391500010325800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000050203163320036080000102004020040200402004020040
8002420039150004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000050202163320036080000102004020040200402004020040
8002420039150004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000050203162320036080000102004020040200402004020040
8002420039150004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000050203163220036080000102004020040200402004020040
80024200391500012425800101080000108000050640000200202003920039999631001980010208000020160000200392003911800221091010800001000050203163320036080000102004020040200402004020040
8002420039150004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000050203163320036080000102004020040200402004020040
8002420039150004025800101080000108000050640000200202003920039999631001980010208000020160000200392003911800211091010800001000050202162320036080000102004020040200402004020040