Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQXTN2 (4S)

Test 1: uops

Code:

  uqxtn2 v0.8h, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230000000612548251000100010003983130301830373037241532895100010002000303730371110011000000000073216112630100030383038303830383038
100430372300000007692539451000100011493983131301830733085241572915114911622000303730851110011000020001863073137112665100030383038303830853038
10043037230011132002932539491008100010003983131301830853037241962915114910322000308530732110011000220122825273140112676100030863038303830383086
1004303723011112880177253945100810081149399670130543037310124153291410001089200030373084211001100020002828095137112630100030383074308530843074
100430732301119001982548491000100810003996700301830853037242582914100011612000308430732110011000202103473124112630100030383038303830843085
10043037231110150002512548251000100010003983131301830373037241532895100010002000303730371110011000000000073116112630100030383038303830383038
10043037230000000612548251000100010003983130301830373037241532895100010002000303730371110011000240022820279116112665100030383038303830863038
100430372211111322407412539251000100011493996701301830743037241962895100010182000303730852110011000000122398079124112665100030853086308530383086
1004307323011112880198254825100010081114398313130183073307324173290211491000232630373085211001100000012528095124112646100030863074303830863038
100430852300111868801982539441008100010003983131301830373037241532895114911612336303730371110011000200002743295124112646100030853074308530383074

Test 2: Latency 1->1

Code:

  uqxtn2 v0.8h, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224002761295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225100251295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250027441295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250018156295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250029761295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225004261295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129696100001003003830038300383003830038
1020430037225003061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225003061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225002761295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)dadbddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500003006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000640216002229630010000103003830038300383003830038
1002430037224000012010329548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000640216002229630010000103003830038300383003830038
1002430037225000012010329548251001010100001010000504277313130018300373003728287328767100102010000222000030037300371110021109101010000100001092640216002229630010000103003830038300383003830038
1002430037244000060010329548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000640216002229630010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300853003728287328767100102010000202000030037300371110021109101010000100001030640216002229630010000103003830038300383003830038
10024300372250000006129548251001010100001010447504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000000640216002229630010000103003830038300383003830038
10024300372250000258010729548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000000640216002229630010000103003830038300383003830038
100243003722500040010329548251001010100001010000504277313130018300373003728287328767100102010000202000030037300841110021109101010000100000000640216002229630010000103003830038300383003830181
100243003722500000027329548251001010100001010000504277313130018300373003728287328767106102010000202000030037300371110021109101010000100000000640316002229630010000103003830038300383003830038
100243003728500000072629548251001010100001010000504277313030162300373003728287328767100102010000202000030037300371110021109101010000100000000640216002229630010000103003830038300383003830181

Test 3: Latency 1->2

Code:

  uqxtn2 v0.8h, v0.4s
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250006129547251010010010000100100005004277160030018300373003728271628741101002001000820020016300373003711102011009910010010000100000001117170160029645100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160130018300373003728271728740101002001000820020016300373003711102011009910010010000100000401117170160029645100001003003830038300383003830038
1020430037225000612954725101001001000010010000500427716003001830037300372827162874110100200100082002001630037300371110201100991001001000010000031291117170160029645100001003003830038300383003830038
10204300372240006129547251010010010000100100005004277160030018300373003728271628741101002001000820020016300373003711102011009910010010000100000401117180160029646100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160030018300373003728271728741101002001000820020016300373003711102011009910010010000100000101117180160029645100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160130018300373003728271728740101002001000820020016300373003711102011009910010010000100000101117180160029646100001003003830038300383003830038
10204300372240006129547251010010010000100100005004277160130018300373003728271728740101002001000820020016300373003711102011009910010010000100000401117170160029646100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160030018300373003728271728740101002001000820020016300373003711102011009910010010000100000131117180160029646100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160130018300373003728271628741101002001000820020016300373003711102011009910010010000100000301117170160029645100001003003830038300383003830038
10204300372250006129547251010010010000100100005004277160030018300373003728271628741101002001000820020016300373003711102011009910010010000100000201117170160029645100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372251000612954725100101010000101000050427716013001830037300372828603287671001020100002020000300373003711100211091010100001010000640216222962910000103003830038300383003830038
100243003722500067262954725100101010000101000050427716013001830037300372828603287671001020100002020000300373003711100211091010100001000000640216222962910000103003830038300383003830038
10024300372250001836312954725100101010000101000050427716013001830037300372828603287671001020100002020000300373003711100211091010100001000000640216222962910000103003830038300383003830038
10024300372250000612954725100101010000101000050427716013001830037300372828603287671001020100002020000300373003711100211091010100001000000640216222962910000103003830038300383003830038
100243003722500007262954725100101010000101000050427716013001830037300372828603287671001020100002020000300373003711100211091010100001000000640216222962910000103003830038300383003830038
100243003722500005362954725100101010000101000050427716013001830037300372828603287671001020100002020000300373003711100211091010100001000000640216222962910000103003830038300383003830038
100243003722400006312954725100101010000101000050427716013001830037300372828603287671001020100002020000300373003711100211091010100001000000640216222962910000103003830038300383003830038
100243003722500002512954725100101010000101000050427716013001830037300372828603287671001020100002020000300373003711100211091010100001000000640216222962910000103003830038300383003830083
10024300372250000612954725100101010000101000050427716013001830037300372828603287671001020100002020000300373003711100211091010100001000000640216222962910000103003830038300383003830038
10024300372250000612954725100101010000101000050427716013001830037300372828603287671001020100002020000300373003711100211091010100001000000640216222962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uqxtn2 v0.8h, v8.4s
  movi v1.16b, 0
  uqxtn2 v1.8h, v8.4s
  movi v2.16b, 0
  uqxtn2 v2.8h, v8.4s
  movi v3.16b, 0
  uqxtn2 v3.8h, v8.4s
  movi v4.16b, 0
  uqxtn2 v4.8h, v8.4s
  movi v5.16b, 0
  uqxtn2 v5.8h, v8.4s
  movi v6.16b, 0
  uqxtn2 v6.8h, v8.4s
  movi v7.16b, 0
  uqxtn2 v7.8h, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420091151110292580116100800161008002850064019620045200652006561280128200800282001600562006520065111602011009910010016000010000001111011911611200621600001002006620066200662006620066
16020420065150110292580116100800161008002850064019620045200652006561280128200800282001600562006520065111602011009910010016000010000001111011911611200621600001002006620066200662006620066
16020420065150110292580116100800161008002850064019620045200652006561280128200800282001600562006520065111602011009910010016000010000001111011911611200621600001002006620066200662006620066
16020420065150110292580116100800161008002850064019620045200652006561280128200800282001600562006520065111602011009910010016000010002001111011911611200621600001002006620066200662006620066
16020420065150110292580116100800161008002850064019620045200652006561280128200800282001600562006520065111602011009910010016000010000001111011911611200621600001002006620066200662006620066
16020420065151110292580116100800161008002850064019620045200652006561280128200800282001600562006520065111602011009910010016000010002001111014311611200621600001002006620066200662006620066
160204200651511102192580116100800161008002850064019620045200652006561280128200800282001600562006520065111602011009910010016000010003001111011911611200621600001002006620066200662006620066
16020420065150110292580116100800161008002850064019620045200652006561280128200800282001600562006520065111602011009910010016000010000001111011911611200621600001002006620066200662006620066
16020420065150110292580116100800161008002850064019620045200652006561280128200800282001600562006520065111602011009910010016000010000001111011911611200621600001002006620066200662006620066
160204200651501102925801161008001610080028500640196200452006520065612801282008002820016005620065200651116020110099100100160000100022031111011911611200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6erob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242007715010000163318001010800001080000506400001102004320062200620322800102080000201600002006220062111600211091010160000100091004516423036322142520059412160000102006320063203272009020063
160024200621500100015129800101080000108000050640000110200432006220062032280010208000020160000200622006211160021109101016000010000100506222449342252520059412160000102006320063202732008920063
1600242006215001100069298001010800001080000506400001102004320062200620322800102080000201600002006220062111600211091010160000100101005216643036322172820059412160000102006320063203022009020063
16002420062150023001632980010108000010800005064000011020043200622006203228001020800002016000020062200621116002110910101600001001701005216622736322172820059412160000102006320063202642008920063
1600242006215002200163298001010800001080000506400001102004320062200620322800102080000201600002006220062111600211091010160000100001004816622236322281320059412160000102006320063202702008720063
1600242006215002200083428001010800001080000506400001102004320075200620322800102080000201600002006220062111600211091010160000100001005416622736322272820059412160000102006320063202692008920063
1600242007115002100163298001010800001080000506400001102004320062200620322800102080000201600002006220062111600211091010160000100431501005416632836322272720059412160000102006320063202672008920063
16002420062151033001753180010108000010800005064000011020043200622006203228001020800002016000020062200621116002110910101600001004631006016622749322212320059415160000102006320063202832008920063
1600242006215002200189298001010800001080000506400001102004320062200620322800102080000201600002006220062111600211091010160000100314701005116622836322272520059412160000102006320063202512008920063
1600242006215103201621633180010108000010800005064000011020043200622006203228001020800002016000020062200621116002110910101600001000721003816622036322281720059412160000102006320063202632008920063

Test 5: throughput

Count: 16

Code:

  uqxtn2 v0.8h, v16.4s
  uqxtn2 v1.8h, v16.4s
  uqxtn2 v2.8h, v16.4s
  uqxtn2 v3.8h, v16.4s
  uqxtn2 v4.8h, v16.4s
  uqxtn2 v5.8h, v16.4s
  uqxtn2 v6.8h, v16.4s
  uqxtn2 v7.8h, v16.4s
  uqxtn2 v8.8h, v16.4s
  uqxtn2 v9.8h, v16.4s
  uqxtn2 v10.8h, v16.4s
  uqxtn2 v11.8h, v16.4s
  uqxtn2 v12.8h, v16.4s
  uqxtn2 v13.8h, v16.4s
  uqxtn2 v14.8h, v16.4s
  uqxtn2 v15.8h, v16.4s
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400603000000942516010810016000810016002050012801321400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000001111011821622400361600001004004040040400404004040040
160204400393000000302516010810016000810016002050012801321400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000030001111011811621400361600001004004040040400404004040040
160204400392990000302516010810016000810016002050012801321400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000001111011821621400361600001004004040040400404004040040
1602044003930000006952516010810016000810016002050012801321400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000001111011821621400361600001004004040040400404004040040
160204400393000000302516010810016000810016002050012801321400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000001111011821621400361600001004004040040400404004040040
160204400393010000302516010810016011210016002050012801321400204034440039199776199901601202001600322003200644003940039111602011009910010016000010000000001111011811622400361600001004004040040400404034840040
160204400393020000302516021010016020910016002050012801321405024045740660200896420315161354202161250200322730403614071614116020110099100100160000100000605615211110327215351403301600001004071540653406624066140650
1602044039630513131719123223662841613871011612741021612665331290628140545407654071220053622025916145620016136420032291440665405011511602011009910010016000010004214001111011821621400361600001004004040040400404004040040
160204400392990000302516010810016000810016002050012801321400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000001111011811622400361600001004004040040400404004040040
160204400393000000302516010810016000810016002050012801321400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000001111011811622400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244005030010009462516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940039111600211091010160000100330010022821161621161240036155160000104004040040400404004040040
1600244003930000000462516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940039111600211091010160000100000100228417162115740036155160000104004040040400404004040040
16002440039299000004625160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000001002284171621113840036155160000104004040040400404004040040
16002440039300000004625160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000001002285161621161340036155160000104004040040400404004040040
160024400393000000046251600101016000012160000501280000015400204003940039199963200191600102016000020320000400394003911160021109101016000010000010024116261642256400363010160000104004040040400404004040040
16002440039300000004625160010101600001016000050128000001540020400394003919996320019160010201600002032000040039400391116002110910101600001001001002411626164214640036305160000104004040040400404004040040
1600244003929900000522516001010160000101600005012800000154002040039400391999632001916001020160000203200004003940039111600211091010160000100000100241162101642285400363010160000104004040040400914004040040
160024400393000000052251600101016000010160000501280000015400204003940039199963200191600102016000020320000400394003911160021109101016000010000010024116281642266400361510160000104004040040400404004040040
160024400393000000052251600101016000010160000501280000015400204003940039199963200191600102016000020320000400394003911160021109101016000010000010024116213164226540036305160000104004040040400404004040040
160024400392990000052251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000010024116271642257400363010160000104004040040400404004040040